Patents Assigned to Blaze DFM, Inc.
  • Gate-length biasing for digital circuit optimization
    Patent number: 7441211
    Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: October 21, 2008
    Assignee: Blaze DFM, Inc.
    Inventors: Puneet Gupta, Andrew B Kahng