Abstract: A method of compensating interference of received symbols in a MIMO OFDM receiver employs MMSE equalization and LLR scaling, and a MIMO OFDM receiver includes a linear MMSE equalizer. The method provides a low-complexity, numerically robust method for compensating interference of received symbols and provides a low-cost, robust digital baseband receiver for MIMO-OFDM, achieved by merging linear MMSE equalization and scaling of the corresponding equalized symbols into a single algorithm that, for the 2×M MIMO case, completely avoids computationally extensive matrix inversion and allows for significant simplification of symbol detection as compared to separate equalization and scaling.

Abstract: A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end, and is generally applicable with handshake-type bus protocols. The clock domain separation module allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation.

Abstract: A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is provided. After a data word has been sent, a synchronizer in the transmitting data processing unit collects an acknowledge signal from each of the receiving data processing units and then generates an indication that the next data word can be transmitted. This allows to speed-up data delivery to parallel working processing units in a system-on-a-chip since data delivery has no longer to account for a maximum predictable latency of the respective receiving units.

Abstract: A method and an activity tracking device for controlling clock gating of a data processing block is provided. The processing block is one of a plurality of data processing blocks of a circuitry system interconnected by a streaming data bus. The activity tracking device receives a busy indication from processing units and streaming data bus segments of the data processing block to keep track of the data transfer and processing activity therein, and has an output connected to a clock gate at the root of the local clock distribution network of the data processing block to gate off the clock of the data processing block when an idle condition is detected, and to recover the clock when a wake-up condition is detected. This provides a low complexity way of automatic clock gating in SoC designs, and generally a way to reduce power consumption of electronic devices.

Abstract: A LTE compliant RF transceiver includes at least one transmit path and at least two receive paths. A switching arrangement connected between a transmit PLL synthesizer and at least one transmit path as well as between a receive PLL synthesizer and at least two receive paths allows the transmit PLL synthesizer to selectively be connected to the receive side of the transceiver as well as the receive PLL synthesizer to selectively be connected to the transmit side of the transceiver, thereby considerably increasing flexibility of the RF transceiver which enables both speed-up of handover procedures and power savings. A modem including the transceiver is also provided.

Abstract: A method for transferring data between a data source and a data sink which are controlled by a common clock provides a handshake-based streaming data protocol for intra-circuitry data transfer between and through functional units of a system built in an integrated circuit.

Abstract: A modem device for use in a wireless communications terminal comprises a plurality of functional units to perform signal processing tasks which are connected in a ring structure. Each of the functional units comprises a local processor, a plurality of hardware accelerators and a switching matrix connected between a data input of the respective functional unit and each of the sub-components. The local processor receives task instructions from a controller of the modem device over a first bus system that uses a first protocol which includes addressing, and in response to the task instructions configures the hardware accelerators and switches the switching matrix to selectively produce connections between the data input and the hardware accelerators in a manner to perform the intended task. Data flow occurs in a ring structure between said functional units and through each of the functional units using a second protocol without addressing.

Abstract: A method is provided for decoding data packets in wireless communication schemes that use a Hybrid Automatic Repeat Request technique, and a receiver for wireless communication that performs such a method. The HARQ memory incorporated in a receiver for wireless communication is minimized to a size which only reserves memory for an average number of erroneous sub-packets. Following decoding, an error check is performed on a per sub-packet basis, and only the softbits of those sub-packets for which decoding errors have been detected are stored in the HARQ memory. Correctly decoded sub-packets are stored in a separate memory. This significantly decreases the size of the HARQ memory required at the receiver which is beneficial in terms of both silicon area and power consumption.

Abstract: Methods and apparatus for uplink data transmission in a Long Term Evolution (LTE) compliant communication system use beam-forming in the uplink to increase the range of LTE compliant wireless communication terminals. Methods are provided for steering the beam in an optimal direction towards the base station, both for time division duplex (TDD) and frequency division duplex (FDD) communication schemes.

Abstract: A method of compensating interference of received symbols in a MIMO OFDM receiver employs MMSE equalization and LLR scaling, and a MIMO OFDM receiver includes a linear MMSE equalizer. The method provides a low-complexity, numerically robust method for compensating interference of received symbols and provides a low-cost, robust digital baseband receiver for MIMO-OFDM, achieved by merging linear MMSE equalization and scaling of the corresponding equalized symbols into a single algorithm that, for the 2×M MIMO case, completely avoids computationally extensive matrix inversion and allows for significant simplification of symbol detection as compared to separate equalization and scaling.