Abstract: A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.

Abstract: A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.

Abstract: A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use with clock signals. Using the clock data type, and other requirements of a circuit specification, clock domain crossing between domains of clocks of the same clock family is handled implicitly. For clock domain crossing between clock domains driven by clocks of different clock families, a “hardware approach” and a “linguistic approach” are provided. A “hardware approach” provides facilities to explicitly specify a synchronizer, using, in part, TRS rules. A “linguistic approach” allows a designer to abstracts the instantiation of synchronizers and instead specify a circuit specification in terms of differently clocked interfaces.

Abstract: A system and method for Term Rewriting System hardware design employs a scheduler that incorporates a preference order in scheduling conflicting rules. The scheduler schedules a conflicting rule to execute when its predicate is true, and it is preferred over other conflicting rules in the preference order. The preference order may be, in one embodiment, a user-specified preference order enumerated by a designer. Such an order may be chosen according to efficiency criteria, such that the conflicting rule most essential for efficient hardware will be scheduled to execute on a given state rather than less essential conflicting rules The system and method advantageously permits a schedule to be computed in a time frame polynomially related to the number of rules, and produces more predictable and more easily understood schedules than conventional methods.

Abstract: A system and method for simulating a digital circuit uses scheduling information for Term Rewriting System (TRS) rules to limit the computation of simulation values to only those value used by the rules scheduled to execute on the current state of the system. Typically only a small subset of TRS rules are scheduled to execute on any given state, thus only values related to this subset are computed. Such a determination may be made by leveraging the logical separation of rule activations and rule actions in a TRS system, such that only rule activation information need be examined.