Abstract: A cascade charge coupled delay circuit including a plurality of serial delay line sections formed on a single semiconducter wafer, said delay line sections being directly coupled to one another through the wafer and means for independently clocking each section of said lines.
Type:
Grant
Filed:
July 1, 1976
Date of Patent:
May 1, 1979
Assignee:
Board of Trustees of the Leland Stanford Jr. Unv.
Inventors:
John D. Shott, Roger D. Melen, James D. Meindl