Abstract: The amount of processor resources and processor-memory bandwidth needed to perform certain memory operations over blocks of memory locations is reduced by supporting macro memory instructions. An intelligent memory controller is operatively connected to one or more processors and to at least one memory. The intelligent memory controller receives macro memory instructions sent from one or more of the processors and translates the macro memory instructions into corresponding sequences of atomic memory instructions to be executed by a memory. While the intelligent memory controller manages execution of the corresponding sequence of atomic memory instructions, the processor which issued the macro memory instruction may continue doing useful work not relying on the result or affected locations of the macro memory instruction.