Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.

Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively effectuate execution of instructions of multiple ISA. In some embodiments, execution of the instructions of the different ISA are effectuated by selectively executing primitive operations (POP) of different ISA implementing POP collections. In some embodiments, the processor further includes at least one ISA selector accessible to the control logic to facilitate the control logic in controlling the datapath to selectively effectuate execution of the instructions of the different ISA. In some embodiments, the processor further includes an ISA library, storing and supplying, e.g. different collections of primitive operations implementing instructions of the different ISA, and logical to physical mappings of the different ISA.

Abstract: A pin control unit and a plurality of addressable storage locations are provided to an integrated circuit to control the input/output (I/O) pins of a functional block of the integrated circuit or the I/O pins of the integrated circuit. Multiple ones of the addressable storage locations are correspondingly coupled to I/O buffers associated with the I/O pins. The pin control unit selectively loads bit values into appropriate ones of the addressable storage locations. In response, the I/O buffers input bit values from and/or output bit values to the corresponding I/O pins. The pin control unit controls subsets of the I/O pins in a coordinated manner as I/O ports. The pin control unit also controls data movement between the addressable storage locations and various temporary storage elements of the functional block/integrated circuit.

Abstract: One or more sets of one or more cache lines of cache locations of an apparatus, such as a processor, a system embedded with a processor, and the like, are dynamically operated at the same or different time periods as different register sets to supply source operands and to accept destination operands for instruction execution. The different register sets may be of the same or of different virtual register files, and if the different register sets are of different virtual register files, the different virtual register files may be of the same or of different architectures. The cache locations implementing the registers may be directly accessed using cache addresses or content addressed using memory addresses.

Abstract: An apparatus employing a cache memory based approach to instruction execution includes a cache memory and one or more control units. The control units operate the cache memory to directly supply appropriate ones of a plurality of values stored in selected ones of said cache locations for a plurality of variables to one or more arithmetic logic units (ALU) as inputs to arithmetic/logic operations, and/or to directly accept and store results of arithmetic logic operations from the one or more ALU as values of the variables in selected ones of said cache locations. The direct supplying and the direct accepting and storing are performed responsive to instructions specifying said arithmetic/logic operations and logically designating the variables associated with the specified arithmetic/logic operations.