Patents Assigned to Breker Verification Systems
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Patent number: 11748240Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: November 3, 2020Date of Patent: September 5, 2023Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 11113184Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: May 19, 2016Date of Patent: September 7, 2021Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 11055212Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: August 27, 2019Date of Patent: July 6, 2021Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 10838006Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: June 27, 2019Date of Patent: November 17, 2020Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 10429442Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: June 13, 2017Date of Patent: October 1, 2019Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 10365326Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two module representations of the plurality of module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the plurality of module representations, and the one or more connections. The test scenario model includes a path from the input via the plurality of module representations and the one or more connections to the desired output.Type: GrantFiled: January 11, 2018Date of Patent: July 30, 2019Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9874608Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed by components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: April 26, 2017Date of Patent: January 23, 2018Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9689921Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: February 26, 2016Date of Patent: June 27, 2017Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9651619Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: March 25, 2016Date of Patent: May 16, 2017Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9360523Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: April 17, 2015Date of Patent: June 7, 2016Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9316689Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: April 17, 2015Date of Patent: April 19, 2016Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 9310433Abstract: A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.Type: GrantFiled: April 17, 2015Date of Patent: April 12, 2016Assignee: Breker Verification SystemsInventors: Adnan Hamid, Kairong Qian, Kieu Do, Joerg Grosse
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Patent number: 7849425Abstract: A method, system and apparatus for constructing a comprehensive test plan for a design under test (DUT) using a hierarchy of goals to generate test cases are provided. Embodiments of the present invention provide for automatically generating a first test case of the test plan from the goal hierarchy by traversing a path from a starting goal to an ending goal, wherein a first goal in the path has a first definition for one or more of a slot and a method. The ending goal of will then assume the first definition of the slot or method, as needed. A further aspect of the invention is generating a second test case by traversing a second path through the hierarchy. If the second path involves traversing a second goal with a second definition of the slot or method, then the ending goal will assume the second definition of the slot or method, as needed.Type: GrantFiled: September 11, 2007Date of Patent: December 7, 2010Assignee: Breker Verification Systems, Inc.Inventors: Adnan A. Hamid, Arthur D. Flatau
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Patent number: 7823100Abstract: A method, system and apparatus for constructing a comprehensive test plan for a design under test (DUT) using a case analysis graph is provided. Embodiments of the present invention provide for automatically generating test cases of the test plan from the case analysis graph by traversing paths through the case analysis graph to select a sequence of components to be exercised by a DUT. Selection of the components is constrained by one or more rules. The rules, in aspects of the invention, provide for selection of specified components to be included in the sequence of components.Type: GrantFiled: September 11, 2007Date of Patent: October 26, 2010Assignee: Breker Verification Systems, Inc.Inventors: Adnan A. Hamid, Arthur D. Flatau
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Patent number: 7779374Abstract: A method, system and apparatus for constructing a comprehensive test plan using a case analysis graph is provided. Embodiments of the present invention further provide for automatically generating test cases from a case analysis graph and for measuring functional coverage of the test cases. Additional embodiments of the present invention provide for visualizing both the comprehensive test plan and functional coverage data.Type: GrantFiled: August 21, 2007Date of Patent: August 17, 2010Assignee: Breker Verification Systems, Inc.Inventors: Adnan A. Hamid, Arthur D. Flatau