Abstract: A noise reduction system having a multiple number of parallel inputs amplifies a low level input signal and reduces noise. The noise reduction system includes an analog averaging circuit connected to the parallel inputs for amplifying the input signals and combining the parallel amplified input signals to generate an output signal. The parallel amplified input signals are examined for polarity by a digital logic averaging circuit. If all the parallel amplified input signals are positive or negative, respectively, the digital logic averaging circuit generates a coincidence signal. The coincidence signal then is used to adjust the gain of a variable gain amplifier connected to the output of the analog averaging circuit. The variable gain amplifier therefore amplifies those portions of the output signal of the analog averaging circuit corresponding to the true low level input signal.