Patents Assigned to BRIDGE SEMICONDUCTOR CORP.
  • Patent number: 11291146
    Abstract: The leadframe substrate mainly includes a modulator, a plurality of metal leads, a resin layer and a crack inhibiting structure. The resin layer provides mechanical bonds between the modulator and the metal leads disposed about peripheral sidewalls of the modulator. The crack inhibiting structure includes a continuous interlocking fiber sheet that covers the modulator/resin interfaces, so that the segregation induced along the modulator/resin interfaces or cracks formed within the resin layer can be prevented or restrained from extending to the top surfaces, thereby ensuring the signal integrity of the flip chip assembly.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 29, 2022
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10804205
    Abstract: The interconnect substrate mainly includes a stiffener, a core layer, a warp balancer and a routing circuitry. The stiffener has an elastic modulus higher than 100 GPa and is laterally surrounded by the core layer. The warp balancer is disposed over the top surface of the core layer and laterally surrounds a cavity aligned with the stiffener. The routing circuitry is disposed under the bottom surfaces of the stiffener and the core layer and electrically connected to the stiffener. By the high modulus of the stiffener, local thermo-mechanical stress induced by un-even thickness can be counterbalanced. Furthermore, adjusting the ratio of the stiffener thickness to the cavity dimension can maintain the cavity area stiffness and modulate the global flatness.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 13, 2020
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10546808
    Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: January 28, 2020
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10446526
    Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 15, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10269722
    Abstract: A wiring board includes an electronic component laterally surrounded by a leadframe, and first and second buildup circuitries disposed beyond the space laterally surrounded by the leadframe and extending over the leadframe. The electronic component includes a first routing circuitry, an encapsulant, optionally an array of vertical connecting elements and optionally a second routing circuitry integrated together. The first routing circuitry provides primary routing for the semiconductor device, whereas the first and second buildup circuitries not only provides further routing, but also mechanically binds the electronic component with the leadframe. The leadframe provides electrical connection between the first buildup circuitry and the second buildup circuitry.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: April 23, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10242964
    Abstract: The wiring substrate includes a cavity and a plurality of vertical connecting channels disposed around the cavity. The vertical connecting channels are bonded with a resin compound and electrically connected to a routing circuitry or a conducting layer under the cavity. The bottom of the cavity is covered by a dielectric layer of the routing circuitry or the resin compound, and an aperture is formed through the dielectric layer of the routing circuitry or the resin compound to be communicated with the cavity. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the routing circuitry or the conducting layer by bonding wires extending through the aperture.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 26, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10211067
    Abstract: The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and electrically connected to a buildup circuitry or a re-distribution layer under the cavity. The bottom of the cavity is covered by a dielectric layer of the buildup circuitry or the resin compound, and an aperture is formed through the dielectric layer of the buildup circuitry or the resin compound to be communicated with the cavity. As a result, a semiconductor device can be face-down disposed in the cavity and electrically connected to the buildup circuitry or the re-distribution layer by bonding wires extending through the aperture.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: February 19, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORP.
    Inventors: Charles W. C. Lin, Chia-Chung Wang