Abstract: This specification discloses a non-volatile static random access memory (SRAM) cell with the feature of keeping data even after the power is turned off. It includes a static random access unit and a non-volatile memory unit. Therefore, it has the random access property of the SRAM normally. After the power is turned off, it can store data in the non-volatile memory unit, so that the data can be automatically restored to the static random access unit from the non-volatile memory unit when the power is turned on.

Abstract: A new memory cell combination is disclosed. It includes a static random access memory (SRAM) unit and a mask read only memory (MROM) unit. The prior art separates the two memory units in different areas on a chip so that the circuit layout is not optimized. The disclosed cell combines them in the same area, saving more than 20% of the area.

Abstract: A refresh-free ultra-low power pseudo dynamic random access memory (DRAM). A clock that controls a DRAM is used to perform 1-bit read, 1-bit write, or a non-read and non-write operation. The clock includes a first read signal, a first write signal, or a first non-read and non-write signal. An interface circuit generates a second read signal, a second write signal, or a second non-read and non-write signal according to the first read signal, the first write signal, or the first non-read and non-write signal, respectively. A static random access memory (SRAM) cell is coupled with the interface circuit for performing the 1-bit read according to the second read signal, the 1-bit write according to the second write signal, or the non-read and non-write operation according to the non-read and non-write signal.

Abstract: A variable voltage tolerant input/output circuit, wherein a leakage current is not produced while having a high reliability, characterized in that the circuit includes a clamping circuit for clamping the N-well potential of M1. When the supply voltage VCC is higher than or equal to the input/output voltage VI/O, the N-well potential of M1 is clamped to the supply voltage VCC; when the supply voltage VCC is lower than the input/output voltage VI/O, the N-well potential of M1 is clamped to the input/output voltage VI/O.

Abstract: The present invention relates to a method for forming a static random access memory (SRAM) cell. In order to avoid constantly reducing operating voltage of the SRAM cell affecting the unit stability and noise jamming of the SRAM cell during read/write processes, the invention employs different thicknesses of gate oxide layers of an access transistor and a pull down transistor. Thereby, not only the &bgr; ratio is increased, but also the unit area is decreased.