Abstract: A telephone jack apparatus which includes a jack body having a plug opening in a front face thereof, terminals in a rear face of the jack body electrically conductively connected to corresponding spring contacts in the plug opening and adapted to receive and conductive association associated respective wires of a telephone cable. a plate affixed to the jack body provides a means for affixing the body to a suitable wall support or receptacle. The entire structure can be installed in a unfinished wall and then after the wall has been completed, a cover plate simply affixed over the socket to complete the installation.

Abstract: A full-fluxed, single-ended, DC converter is disclosed. The converter includes a transformer having primary and secondary windings magnetically coupled and wound about a common core. A regulation switch is connected in series with the primary winding and allows the primary current to be interrupted in a time-controlled fashion, causing the desired output characteristics to be achieved. The series combination of a storage capacitor and reset switch are provided in parallel with the regulation switch to initiate bidirectional magnetizing current flow in the primary winding and, hence, bidirectional flux excursions in the transformer core. As a result, power transfer characteristics are improved. In the preferred embodiment, the regulation and reset switches are complementary field effect transistors (FETs) whose sources and gates are tied together allowing their gates to be coupled to a single bipolar drive signal.

Abstract: A selected one of a plurality of unique N-bit digital code words that corresponds to an associated signaling message is continuously transmitted until it is desired to transmit a different signaling message. Decoder logic in the receiver looks at a new group of N-signaling bits during each signaling bit interval, without reference to the start of a transmitted code word, and makes a decision during each signaling bit interval as to what signaling message was transmitted. In this manner a keep-alive signal is virtually continuously provided in the receiver. Latch circuitry repeats the previous decision from the decoder logic when the current group of N-signaling bits does not correspond to one of the unique code words or an ordered permutation thereof. In an alternate embodiment a memory circuit requires that the decoder logic repeat the same decision as to what signaling message was transmitted for P consecutive groups of N-signaling bits (i.e.

Abstract: A selected one of a plurality of unique N-bit digital code words that corresponds to an associated signaling message is continuously transmitted until it is desired to transmit a different signaling message. Decoder logic in the receiver looks at a new group of N-signaling bits during each signaling bit interval, without reference to the start of a transmitted code word, and makes a decision during each signaling bit interval as to what signaling message was transmitted. In this manner a keep-alive signal is virtually continuously provided in the receiver. Latch circuitry repeats the previous decision from the decoder logic when the current group of N-signaling bits does not correspond to one of the unique code words or an ordered permutation thereof. In an alternate embodiment a memory circuit requires that the decoder logic repeat the same decision as to what signaling message was transmitted for P consecutive groups of N-signaling bits (i.e.

Abstract: The modulator comprises a serial to parallel converter which separates alternate bits of a serial-binary data stream into I and Q bit streams that are stored in associated shift registers, a pair of ROMs that drive associated D/A converters, and a quadrature-phase modulator. Each bit of the I and Q bit streams has a duration of 2T, where T is the bit interval or period of a data bit. Each of the ROMs comprises blocks of memory that contain a plurality of digital words. The present and immediate past I and Q bits in the shift registers, and a baud clock signal of one-half the data signal rate, are applied to address inputs of the ROMs for selecting associated memory blocks in the 2 ROMs. A counter then clocks the ROMs for sequentially outputting the contents of the addressed memory blocks to the converters which produce analog voltages that phase modulate a carrier signal for moving a resultant signal vector with a constant envelope during each bit interval.

Abstract: In a mobile radiotelephone system, N separate modulated carrier signals in N frequency channels are applied to a demodulating radio receiver which provides a succession of N different output signals each having idle and busy states. An idle and signal-to-noise detector monitors each of the output signals of the radio receiver. The detector provides a first logic signal when one of the output signals concurrently exhibits an idle state and has at least a predetermined minimum signal-to-noise level, and provides a second logic signal at all other times. A receiver switching circuit, in response to the second logic signal, causes the receiver to cyclically switch to each of the N frequency channels. When the receiver switches to a carrier signal which causes the detector to produce a first logic signal, the switching circuit causes the receiver to lock onto that particular carrier signal.