Abstract: A system and method for accelerating the performance of finite impulse response (FIR) filtering operations in a processor system. The system and method accelerates FIR filtering operations by using a holding register to provide additional input samples to an instruction beyond those normally accommodated by source registers, and by using a large number of multipliers that can operate in parallel on the input samples in order to generate output sample of a FIR filter, such as a non-decimating FIR filter.