Abstract: Aspects of a method and system for a delta quantizer for MIMO pre-coders with finite rate channel state information feedback may include quantizing a change in channel state information in a MIMO pre-coding system onto a codebook, which comprises one or more unitary matrices, using a cost function. The codebook may be generated based on at least the channel state information. The channel state information may comprise a matrix V and the cost function f(A) may be defined by the following relationship: f ? ( A ) = ( 1 N ? ? j = 1 N ? ? a jj ? 2 ) where A is a matrix of size N by N and aij is element (i,j) of matrix A. One or more unitary matrices may be generated from at least a first set of matrices and a second set of matrices, where the first set of matrices may comprise one or more Givens matrices. A dynamic range and a resolution of the codebook may be modified.

Abstract: Aspects of a method and system for processing signals in a high performance receive chain may include amplifying radio frequency signals in amplifier chains in a multistandard radio frequency front-end, comprising one or more shared processing stages, and combining, with substantially equal gain, a number of phase-shifted radio frequency signals of the radio frequency signals into substantially equal-gain-combined radio frequency signals. The substantially equal-gain-combined radio frequency signals may be demodulated to obtain inphase channels and quadrature channels. A number of inphase channels and quadrature channels may be processed in I-channel processing blocks and Q-channel processing blocks to generate an output analog baseband signal. The multistandard radio frequency front-end may be capable of processing Bluetooth® signals and Wireless Local Area Network (WLAN) signals.

Abstract: Aspects of a method and system for polar modulation with discontinuous phase for RF Transmitters with power control may include performing by one or more circuits comprising a plurality of amplifiers, configuring one or more of the plurality of amplifiers to provide a coarse amplitude gain and a power level gain. One or more remaining ones of the plurality of amplifiers may be configured to provide an amplitude offset gain, and a signal may be amplified utilizing a combined gain provided by the one or more of the plurality of amplifiers and by the one or more remaining ones of the plurality of amplifiers. The signal may comprise modulated RF signal, and/or a phase modulated RF signal. An RF carrier signal may be modulated to generate the signal.

Abstract: Secure communication of information in a communication network may comprise acquiring a security code from a second communication device by a first communication device and receiving media containing the security code such as a pin code from the first communication device. The security code may be translated into an IP address corresponding to the second communication device. The received media may be routed to the second communication device based on the IP address of the second communication device. In this regard, the IP address of the second communication device remains anonymous or unknown to the first communication device. A duration for which the security code is valid may be limited to a specific time period and/or for a particular number of uses. Notwithstanding, the security code may be acquired out-of-band.

Abstract: Aspects of a method and system for a high-precision frequency generator using a direct digital frequency synthesizer for transmitters and receivers may include generating a second signal from a first signal by frequency translating an inphase component of the first signal utilizing a high-precision oscillating signal that may be generated using at least a direct digital frequency synthesizer (DDFS) and at least a Phase-Locked Loop (PLL). A corresponding quadrature component of the first signal may be frequency translated utilizing a phase-shifted version of the high-precision oscillating signal. The inphase component of the first signal may be multiplied with the high-precision oscillating signal and the quadrature component of the first signal may be multiplied with the phase-shifted version of the high-precision oscillating signal. The second signal may be generated from the first signal by adding the frequency translated inphase component to the frequency translated quadrature component.

Abstract: Herein described is a system and method for modifying facial video transmitted from a first videophone to a second videophone during a videophone conversation. A videophone comprises a videophone image processing system (VIPS) that stores one or more preferred images. The one or more preferred images may comprise an image of a person presented in an attractive appearance. The one or more preferred images may comprise one or more avatars. Additionally, the VIPS may be used to incorporate one or more facial features of the person into a preferred image or avatar. Furthermore, a replacement background may be incorporated into the preferred image or avatar. The VIPS transmits a preferred image of a first speaker of a first videophone to a second speaker of a second videophone by capturing an actual image of the first speaker and substituting at least a portion of said actual image with a stored image.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: Herein described is a system and method that tracks the face of a person engaged in a videophone conversation. In addition to performing facial tracking, the invention provides stabilization of facial images that are transmitted during the videophone conversation. The face is tracked by employing one or more algorithms that correlate videophone captured facial images against a stored facial image. The face may be better identified by way of employing one or more voice recognition algorithms. The one or more voice recognition algorithms may correlate utterances of the person engaged in a conversation to one or more stored utterances. The identified utterances are subsequently mapped to a stored facial image. In a representative embodiment, the system used for performing facial tracking and image stabilization comprises an image sensor, a lens, an actuator, and a controller/processor.

Abstract: A mobile phone that uses OS virtualization for minimizing power consumption in mobile phones is provided. A mobile phone according to the invention may include a plurality of application stacks and a plurality of processor cores. Each of the application stacks preferably corresponds to one of the plurality of processor cores. The mobile phone also includes a hypervisor. In a first state, the hypervisor allocates tasks from each of the application stacks to the processor core that corresponds to the respective application stack. In a second state, the hypervisor allocates selected tasks from the plurality of application stacks to a single processor core. The second state may be an idle state and the tasks that are allocated to the single processor core may be periodic tasks.

Abstract: The present invention relates to a mobile set integrating a memory efficient data storage system for the real time recording of voice conversations, data transmission and the like. The data recorder has the capacity to selectively choose the most relevant time frames of a conversation for recording, while discarding time frames that only occupy additional space in memory without holding any conversational data. The invention executes a series of logic steps on each signal including a voice activity detector step, frame comparison step, and sequential recording step. A mobile set having a modified architecture for performing the methods of the present invention is also disclosed.

Abstract: This invention provides colored noise detection algorithm(s). This colored noise detection algorithm(s) may be implemented with a multi-branch equalizer processing module that enables interference cancellation when colored noise is associated with received radio frequency (RF) bursts. The noise discriminator identifies when the radio frequency (RF) bursts have white noise or colored noise associated with them. Alternatively the noise discriminator may be able to determine and enable interference cancellation in response to an interference-limited received RF burst as opposed to a noise-limited received RF burst. The multi-branch equalizer improves the signal-to-noise ratio by improving the equalization with a second branch operable to be trained based upon known training sequences and at least partially re-encoded data bits.

Abstract: A single side band transmitter having reduced DC offset includes a current source modulation module, a current mirror module, a 1st mixing module, a 2nd mixing module, a summing module, and a power amplifier. The current source module is operably coupled to modulate, in accordance with a modulation protocol (e.g., FSK) data to produce an in-phase current component and a quadrature current component. The current mirror module is operably coupled to mirror the in-phase current component to produce a mirrored in-phase current component and is also operably coupled to mirror the quadrature current component to produce a mirrored quadrature current component. The 1st mixing module is operably coupled to mix the mirrored in-phase current component with an in-phase current component of a local oscillation to produce a 1st mixed current signal.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A digital high frequency power detection circuit includes a peak detecting circuit and a peak computing circuit. The peak detecting circuit is operably coupled to detect a peak value of a high frequency signal and includes an amplifier, transistor, and capacitor. The amplifier has a 1st input, 2nd input and an output, where the 1st input is operably coupled to receive the high frequency signal. The transistor has a gate, a drain, and a source, where the gate is coupled to the output of the amplifier, the source is coupled to a supply voltage, and the drain is coupled to the 2nd input of the amplifier. The capacitor is operably coupled to the drain of the transistor and to a reference potential. The voltage imposed across the capacitor represents the peak value of the high frequency signal. The peak computing circuit is operably coupled to generate a digital peak value from the peak value.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: The measuring of local oscillation leakage in radio frequency integrated circuits (RFICs) begins by concurrently enabling a transmitter portion and a receiver portion of a radio frequency integrated circuit. The processing then continues by providing a zero input to the transmitter portion such that information contained in the RF signals corresponds to local oscillation leakage produced by the transmitter portion. The processing continues by detecting the concurrent enablement of the transmitter and receiver portions. The processing continues by measuring, via the receiver portion, the received signal strength of the RF signals. The processing continues by processing the received signal strength over a predetermined period of time commencing upon the detection of the concurrent enablement to obtain a measure of the local oscillation leakage.

Abstract: A RFIC includes a die and a package. The die contains a radio frequency (RF) input/output (I/O) section, an RF-to-baseband conversion section, and a baseband processing section. The package includes a plurality of connections for connecting to the die. The die is positioned within the package to minimize adverse affects of parasitics components of coupling the RFIO section to an antenna. The positioning of the die within the package may be offset from the center of the package and/or positioned at the edge of the package.

Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.

Abstract: A linear high powered integrated circuit transmitter includes an up-conversion module, a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The up-conversion module is operably coupled to produce a differential up-converted signal by mixing one or more local oscillations with a low intermediate frequency (IF) signal. The balanced integrated circuit coupling couples the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the up-converted signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a transmit RF signal.

Abstract: A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.