Abstract: A system and method for noise cancellation in a signal-processing circuit (e.g., an analog-to-digital converter circuit). Various aspects of the present invention may comprise inputting a first input signal and a digital input signal to the signal-processing circuit. The digital input signal may, for example, comprise a digital dither signal or other processor control signal. The signal-processing circuit may, for example, output a signal comprising a first signal component that is primarily a function of the first input signal and a second signal component that is primarily a function of the digital input signal. The second signal component may be estimated based on estimated behavior of the signal-processing circuit in response to the digital input signal. The estimated second signal component may, for example, be substantially removed from the signal-processing circuit output signal.

Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Abstract: A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all converging at startup of the system. The operation of the startup protocol is partitioned into stages. The first stage includes the step of converging the equalizer and the timing recovery system of the slave while converging the noise reduction system of the master. Upon completion of the first stage the protocol enters a second stage which includes the step of converging the equalizer and the timing recovery system of the master, converging the noise reduction system of the slave, freezing the timing recovery system of the slave, and resetting the noise reduction system of the master.