Abstract: A reception system includes an antenna that receives and inbound RF signal. An antenna interface includes a low noise amplifier that generates an amplified received signal, based on the inbound RF signal. A transmission path coupled carries the amplified received signal to an integrated circuit, that includes a RF receiver with an RF front end that generates a desired RF signal from the amplified received signal, a down conversion module, that generates a down converted signal from the desired RF signal and a receiver processing module that generates inbound data for at least one communication application.

Abstract: A (radio frequency) RF reception system includes an off-chip antenna interface and an integrated circuit. The an off-chip antenna interface includes at least one first off-chip impedance matching component, a filter, and at least one second off-chip impedance matching component. The integrated circuit includes an on-chip antenna interface that forms a first programmable impedance matching network with the at least one first off-chip impedance matching component, and forms a second programmable impedance matching network with the at least one second off-chip impedance matching component. The first programmable impedance matching network and the second programmable impedance matching network are programmable based on a frequency selection signal.

Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip filter component that forms a programmable filter with the at least one off-chip filter component. The programmable filter is programmable based on a control signal. An RF receiver generates inbound data in response to a received signal from the programmable filter.

Abstract: An on-chip inductor includes a first turn on a first dielectric layer and a via, coupled to the first turn. A second turn on a second dielectric layer, is coupled to the first dielectric layer and via. The first dielectric layer includes at least one removed dielectric section where a portion of the first dielectric is removed between the first turn and the second turn, improving the magnetic coupling between the first turn and the second turn.

Abstract: A voice data and RF integrated circuit (IC) includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions, determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and generates a plurality of power supply signals based on the power mode signal.

Abstract: A device includes a first integrated circuit, a second integrated circuit and an RF bus controller. Each of the first and second ICs includes a radio frequency (RF) bus transceiver. The RF bus controller is coupled to control intra-device RF communications between the RF bus transceivers of the first and second ICs.

Abstract: Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (?) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors.

Abstract: A data scrambling circuit is provided. The data scrambling circuit includes an integrated circuit having a digital logic device and an interface circuit coupled to the digital logic device. Also included is an external memory coupled to output pins on the interface circuit. The digital logic device communicates patterned data to the interface circuit. The interface circuit then scrambles the patterned data to produce a pseudo random output to be stored within the external memory and unscrambled a pseudo random signal from the external memory to produce unscrambled data to be read by the digital logic device.

Abstract: Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).

Abstract: A technique to detect head instability by monitoring for a baseline popping (BLP) noise effect on demodulation bursts read from a disk. In one technique, a digital filter is employed as a moving average filter so that the filtering of the bursts has a zero output from the filter if only the bursts are present. However, when a BLP event occurs, the noise effect causes a non-zero output from the filter. A threshold value is set and when the output of the filter exceeds the threshold value, a BLP indication is noted. Although various filters may be used, in one technique, a filter suitable for use in detecting thermal asperity defects is used for the BLP detection filter.

Abstract: Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation. A novel means is presented herein by which error magnitudes (or error values) can be calculated directly without requiring the generation of an error value polynomial (EVP). Modification of the Koetter decoding approach and the Forney formula are employed herein to perform the direct calculation of the error values. This approach is operable to save computation clock cycles that would normally be used to compute the EVP, and these clock cycles may be used to reduce the otherwise required parallelism and complexity in the ECC design that may be needed to perform the error correction in the allotted time and may also result in power savings. Some advantages related to this may approach include lower risk, less design time, and more scalability in an overall design.

Abstract: Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.

Abstract: A technique to detect defects when reading a defect scan pattern stored on a disk in which the detected defects are processed differently depending on which region of a sector the defect is resident. In one implementation, a mask is used to identify the defects of different regions. By differentiating different regions within the sector for defect scan, sync mark and preamble fields may be treated as critical regions so that different defect scan properties may be attributed when performing the defect scan.

Abstract: An integrated circuit (IC) includes a package substrate, a die, and an antenna structure. The die includes a functional circuit module and a radio frequency (RF) transceiver that processes inbound and outbound RF signals. The antenna structure is coupled to the RF transceiver and is on the die and/or the package substrate. The antenna structure receives the inbound RF signal within a frequency band of approximately 55 GHz to 64 GHz and transmits the outbound RF signal within the frequency band.

Abstract: A low efficiency integrated circuit (IC) antenna includes an antenna element and a transmission line. The antenna element is on a first metal layer of a die and has a length less than approximately one-tenth of a wavelength or greater than one-and-one-half times the wavelength for a frequency band of approximately 55 GHz to 64 GHz. The transmission line is on the die and is electrically coupled to feed points of the antenna element.

Abstract: Angle estimation for modulated signal. A novel compensation technique is presented by which angle estimation may be performed for a modulated signal. More specifically, the angle between a constellation corresponding to a received signal and a constellation corresponding to a received signal may be very efficiently estimated using any one of the possible embodiments corresponding to various aspects of the invention. After this angle has been estimated, the received signal or the expected constellation may be rotated (or de-rotated) to compensate for this angular difference. In doing so, better estimates of the information bits that are demodulated and decoded from the received signal may be made.

Abstract: An integrated circuit (IC) antenna structure includes a die, a package substrate, an antenna element, a ground plane, and a transmission line. The antenna element is on the die and/or package substrate and has a length in the range of approximately 1¼ millimeters to 2½ millimeters. The ground plane has a surface area larger than a surface area of the antenna element. The transmission line is on the die and/or the package substrate and includes a first line and a second line, wherein at least the first line is electrically coupled to the antenna element.

Abstract: An adjustable integrated circuit antenna structure includes a plurality of antenna elements, a coupling circuit, a ground plane, and a transmission line circuit. The coupling circuit is operable to couple at least one of the plurality of antenna elements into an antenna based on an antenna structure characteristic signal, wherein the antenna has at least one of an effective length, a bandwidth, an impedance, a quality factor, and a frequency band in accordance with the antenna characteristic signal. The ground plane is proximal to the plurality of antenna elements. The transmission line circuit is coupled to provide an outbound radio frequency (RF) signal to the antenna and receive an inbound RF signal from the antenna.

Abstract: An integrated circuit (IC) includes a package substrate, a die, and a plurality of antenna structures. The die includes a radio frequency (RF) transceiver and a control module, wherein the RF transceiver processes inbound and outbound RF signals. The control module enables the RF transceiver to receive the inbound RF signal from one or more of the plurality of antenna structures in a frequency band of approximately 55 GHz to 64 GHz and enables the RF transceiver to provide the outbound RF signal to one or more of the plurality of antennas structures for transmission in a frequency band of approximately 55 GHz to 64 GHz.

Abstract: An integrated circuit (IC) antenna structure includes a micro-electromechanical (MEM) area, a feed point, and a transmission line. The micro-electromechanical (MEM) area includes a three-dimensional shape, wherein the three dimensional-shape provides an antenna structure. The feed point is coupled to provide an outbound radio frequency (RF) signal to the antenna structure for transmission and to receive an inbound RF signal from the antenna structure. The transmission line electrically coupled to the feed point.