Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.

Abstract: A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: A multimode wireless communication includes a digital baseband processing module, an analog to digital converter module, a digital to analog converter module, a first radio section, and a second radio section. The digital baseband processing module is operably coupled to convert outbound data into outbound digital baseband signals and to convert inbound digital baseband signals into inbound data. The analog to digital converter module is operably coupled to convert inbound analog baseband signals into the inbound digital baseband signals. The digital to analog converter module is operably coupled to convert the outbound digital baseband signals into outbound analog baseband signals. The first radio section is operably coupled to convert the outbound analog baseband signals into first outbound radio frequency (RF) signals and to convert first inbound RF signals into the inbound analog baseband signals when the wireless communication device is in a first mode of operation.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: Method of processing a transmitted encoded media data stream is received. If a data element arrives prior to, or at, a predetermined playout deadline, the data element is decoded, the media represented by the decoded data element is played, and the data element is provided to a decoder state machine to update a decoder state. If a data element arrives after the predetermined playout deadline, the data element is provided to the decoder state machine to update the decoder state. In one embodiment, if the specified data element fails to arrive by the playout deadline, a subsequently received data element is saved in memory. Then, if the specified data element arrives after the predetermined playout deadline, the specified data element and the saved, subsequently received, data element are provided to the decoder state machine to update the decoder state.

Abstract: A system and method is presented that uses hardware at a central node to determine if bandwidth being provided to a remote node in accordance with an unsolicited grant service (UGS) flow requires adjustment. In one embodiment, the hardware performs this function by comparing information in two consecutively-received UGS extended headers from the same remote device. If the information in the current and previous UGS extended headers differ, then an indication is provided to software of the central node that the bandwidth being provided to the remote node requires adjustment.

Abstract: A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a temperature sensing module that produce accurate voltage level readings may be mapped into corresponding temperature values. A processor, among other actions, adjusts gain level settings based upon detected temperature values. One aspect of the present invention further includes repetitively inverting voltage signals across a pair of semiconductor devices beings used as temperature sensors to remove a common mode signal to produce an actual temperature-voltage curve. In one embodiment of the invention, the circuitry further includes a pair of amplifiers to facilitate setting a slope of the voltage-temperature curve.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.

Abstract: A communication system includes a supervisory node (e.g., a headend) and one or more remote nodes (e.g., cable modems). The supervisory node or a remote node monitors a characteristic associated with the communication system. Remote node transmits an upstream communication among a plurality of physical upstream channels based on the characteristic. The average transmit power used to transmit the upstream communication among the plurality of physical upstream channels is no greater than the average transmit power that would be necessary to transmit the upstream communication using a single physical upstream channel at a lower data rate.

Abstract: Decoding time stamps (DTSS) and presentation time stamps (PTSs) are used in fine granularity scalability (FGS) coding during MPEG-4 video coding. An input video is encoded in an FGS encoder into a base layer bitstream and an enhancement bitstream. The bitstreams are provided over a variable bandwidth channel to an FGS decoder. The DTSs and the PTSs are selected during encoding as to conserve memory during FGS decoding. The video object planes (VOP) in the bitstreams include base VOPs and FGS VOPs, and may also include fine granularity temporal scalability (FGST) VOPs. The FGS VOPs and the FGST VOPs may be organized in the same layer or in different layers. The base VOPs are combined with the FGS VOPs and the FGST VOPs to generate enhanced VOPs.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: A system and method is presented that uses hardware at a central node to determine if bandwidth being provided to a remote node in accordance with an unsolicited grant service (UGS) flow requires adjustment. In one embodiment, the hardware performs this function by comparing information in two consecutively-received UGS extended headers from the same remote device. If the information in the current and previous UGS extended headers differ, then an indication is provided to software of the central node that the bandwidth being provided to the remote node requires adjustment.

Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.