Patents Assigned to Broadcom Corporations
-
Patent number: 7080310Abstract: A method for decoding an algebraic-coded message including determining a discrepancy indicator; determining an error locator polynomial according to a modified Berlekamp-Massey algorithm such that an uncorrectable message is detected; and producing a perceptible indication of the detected uncorrectable message. An apparatus includes storage devices, arithmetic components, and an uncorrectable message detector.Type: GrantFiled: December 11, 2003Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventor: Kelly Cameron
-
Patent number: 7079657Abstract: A system and method are disclosed for performing digital multi-channel decoding of a BTSC composite audio signal. Analog-to-digital conversion is performed on a composite analog audio signal at a fast clock rate to generate a composite digital audio signal at a first sample rate. Digital frequency compensation is performed on the composite digital audio signal at the first sample rate to generate a compensated composite audio signal. Digital channel demodulation and filtering are performed on the compensated composite audio signal at the first sample rate to generate a first single channel audio signal at a second sample rate.Type: GrantFiled: February 26, 2002Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: David Chaohua Wu, Hoang Nhu, Russ Lambert, Alexander G. MacInnis, Ronald Crochiere
-
Patent number: 7079058Abstract: A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.Type: GrantFiled: May 18, 2004Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: Gregory H. Efland, Venkat Kodavati, Gouri Pidugu, Srinivasa H. Garlapati
-
Patent number: 7079599Abstract: A wireless transceiver includes a Radio Frequency (RF) transceiver, a baseband transmitter section, and a baseband receiver section. The baseband receiver section receives a baseband signal from the RF transceiver, extracts data therefrom, and provides the data to a host system. The baseband receiver section includes a programmable gain amplifier, an Analog-to-Digital Converter (ADC), a symbol timing compensation section, an RF carrier compensation section, a decision feedback equalizer section, and a preamble processor. The symbol timing compensation section modifies the samples of the baseband signal to compensate for symbol timing variations between a symbol clock of the wireless device and a symbol clock of a transmitting wireless device. The RF carrier compensation section modifies the samples of the baseband signal to compensate for RF carrier variations between an RF carrier of the wireless device and an RF carrier of the transmitting wireless device.Type: GrantFiled: September 10, 2001Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventor: Jeyhan Karaoguz
-
Patent number: 7078943Abstract: A differential line driver includes a plurality of driver cells. Control logic outputs positive and negative control signals to the driver cells so as to match a combined output impedance of the driver cells at (Vop, Von). Each driver cell includes an input Vip and an input Vin, an output Vop and an output Von, a first PMOS transistor and a first NMOS transistor having gates driven by the input Vip, and a second PMOS transistor and a second NMOS transistor having gates driven by the input Vin. A source of the first PMOS transistor is connected to a source of the second PMOS transistor. A source of the first NMOS transistor is connected to a source of the second NMOS transistor. First and second resistors are connected in series between the first PMOS transistor and the first NMOS transistor, and connected together at Von. Third and fourth resistors are connected in series between the second PMOS transistor and the second NMOS transistor, and connected together at Vop.Type: GrantFiled: January 28, 2005Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: David Seng Poh Ho, Wee Teck Lee
-
Patent number: 7080295Abstract: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying the initial symbol erasure threshold using the initial symbol erasure margin to produce a modified symbol erasure threshold. By then periodically modifying the modified symbol erasure threshold adaptive via updating the symbol erasure threshold and/or symbol erasure margin based on various error quantities, the technique can compensate for time-variant considerations, such as drifting noise levels.Type: GrantFiled: June 5, 2003Date of Patent: July 18, 2006Assignee: Broadcom CorporationInventors: Miguel Peeters, Geert Arnout Albert Goris
-
Publication number: 20060152870Abstract: An I/O ESD protection configuration of an integrated circuit that includes an ESD protection circuit connected between an I/O pad and an internal circuit at a first node and to an inductor at a second node. The inductor is connected between the second node and an external power supply. The external power supply provides a high reverse bias voltage across a diode of the ESD protection circuit. An ESD clamp is connected between the second node and a ground. An ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event. The inductor can be chosen to tune out a parasitic capacitance of the ESD clamp. The inductor can also block high frequency signals between the I/O pad and the external power supply, thereby minimizing the parasitic capacitance of the diode of the ESD protection circuit at high frequency.Type: ApplicationFiled: July 6, 2005Publication date: July 13, 2006Applicant: Broadcom CorporationInventors: Chun-Ying Chen, Agnes Woo
-
Publication number: 20060153307Abstract: A method, system and computer program product to adjust transfer rates on conductors in a multi-conductor cable comprising monitoring signals received on each conductor, determining a Signal to Noise Ratio (SNR) for each conductor and adjusting a transfer rate on one or more conductors based on the corresponding SNR. In an embodiment the multi-conductor cable is a twisted pair Ethernet cable. The method further comprises determining whether a conductor is transmitting at an optimal transfer rate as a function of its SNR, calculating an optimal transfer rate for each conductor as a function of its SNR and periodically measuring a change in SNR on each conductor. If the change in SNR is greater than a predetermined threshold, then the transfer rate is re-calculated for the conductors requiring transfer rate adjustment as a function of SNR.Type: ApplicationFiled: January 12, 2006Publication date: July 13, 2006Applicant: Broadcom CorporationInventors: Kevin Brown, Scott Powell, Gottfried Ungerboeck
-
Patent number: 7076586Abstract: A system may include two or more agents, one of which may be identified as a default agent. If none of the agents arbitrate for the bus, the default agent may be given a default grant of the bus. If the default agent has information to transfer on the bus, the default agent may take the default grant and my transfer the information without first arbitrating for the bus and winning the arbitration. In one embodiment, the default agent may arbitrate for the bus when it has information to transfer and no default grant is received. The default agent may be an equal participant in arbitration. A fair arbitration scheme may thus be implemented in arbitrations in which there is contention for the bus.Type: GrantFiled: October 6, 2000Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: Joseph B. Rowlands, Shailendra S. Desai
-
Patent number: 7075939Abstract: A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.Type: GrantFiled: June 11, 2001Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: Mohan Kalkunte, Shekhar Ambe
-
Patent number: 7075978Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18, 20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude contained in the symbol is detected 28 and compared with a threshold. If the peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated.Type: GrantFiled: August 6, 2001Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventor: Mark Taunton
-
Patent number: 7076232Abstract: A radio transceiver includes amplification circuitry that is coupled to receive a down converted signal and to provide infinite rejection of any DC component added by the down conversion circuitry. Specifically, an amplification stage includes a voltage integrator that is coupled within a feedback loop of the amplification circuitry to produce a DC charge having a magnitude that equals the added DC component but a polarity that is opposite. Accordingly, the voltage produced by the voltage integrator is added to the signal received from the down conversion circuitry to cause the amplification circuitry to merely amplify the wireless communication signals characterized by a frequency of oscillation. Logic circuitry is used for selectively coupling the voltage integrator to an output port of the amplification circuitry.Type: GrantFiled: May 3, 2002Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventor: Hooman Darabi
-
Patent number: 7076034Abstract: Reliable detection of a call-waiting tone is provided by employing a correlation based technique. A modem or other device employing such a technique need not rely on carrier drop detection and is generally insensitive to other energy or noise on the line.Type: GrantFiled: March 8, 2004Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: Haixiang Liang, Zarko Draganic
-
Patent number: 7076582Abstract: A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.Type: GrantFiled: September 24, 2004Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: James Y. Cho, Joseph B. Rowlands, Mark H. Pearce
-
Patent number: 7076226Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.Type: GrantFiled: December 30, 2003Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: Klaas Bult, Rudy van de Plassche, Pieter Vorenkamp, Arnoldus Venes
-
Patent number: 7075980Abstract: A technique is described for reliably determining whether a direct digital connection exists between a transmitting server modem and a receiving client modem. Such a determination is an essential part of the training procedure for modems that conform to ITU-T Recommendation V.90 but is also applicable to other data communications configurations and equipment. In some configurations in accordance with the present invention, segments of a modem training signal, L1L2, are used to make the determination.Type: GrantFiled: November 19, 2002Date of Patent: July 11, 2006Assignee: Broadcom CorporationInventors: Haixiang Liang, Mark Gonikberg
-
Publication number: 20060145762Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.Type: ApplicationFiled: January 5, 2005Publication date: July 6, 2006Applicant: Broadcom CorporationInventor: John Leete
-
Publication number: 20060146950Abstract: A reduced-complexity maximum-likelihood detector that provides a high degree of signal detection accuracy while maintaining high processing speeds. A communication system implementing the present invention comprises a plurality of transmit sources operable to transmit a plurality of symbols over a plurality of channels, wherein the detector is operable to receive symbols corresponding to the transmitted symbols. The detector processes the received symbols to obtain initial estimates of the transmitted symbols and then uses the initial estimates to generate a plurality of reduced search sets. The reduced search sets are then used to generate decisions for detecting the transmitted symbols. In various embodiments of the invention, the decisions for detecting the symbols can be hard decisions or soft decisions.Type: ApplicationFiled: December 31, 2004Publication date: July 6, 2006Applicant: Broadcom CorporationInventor: Min Chuin Hoo
-
Publication number: 20060149953Abstract: A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wherein said operand store defines a plurality of lanes each holding an object, a plurality of operators associated respectively with the lanes for carrying out an operation specified in an instruction on objects in the operand lanes, a destination store for holding objects resulting from the operation on a lane by lane basis, a plurality of control stores each comprising a plurality of indicators to control for each lane whether or not an operation defined in an instruction is to be performed on that lane, and control circuitry for controlling which of said plurality of control stores is to be used to control per lane execution of an instruction, the control circuitry being operative to select a control store from the plurality of control stores basedType: ApplicationFiled: January 9, 2006Publication date: July 6, 2006Applicant: Broadcom CorporationInventor: Sophie Wilson
-
Publication number: 20060145295Abstract: A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.Type: ApplicationFiled: March 2, 2006Publication date: July 6, 2006Applicant: Broadcom CorporationInventor: Liming Tsau