Abstract: The capability to encrypt or compress the traffic over network links, thus improving the security of the link on the performance of the links, and the capability to encrypt/decrypt data stored on the storage devices without requiring specialized hosts or storage devices. In a first embodiment, traffic to be routed over a selected link needing encryption and/or compression is routed to hardware which performs the encryption and/or compression and returned for transmission over the link. A complementary unit at the second end of the link routes the received frames to complementary hardware to perform the decryption and/or decompression. The recovered frames are then routed to the target device in a normal fashion. In a variation of this first embodiment the hardware is developed using an FPGA. This allows simple selection of the desired feature or features present in the switch. The switch can be easily configured to perform encryption, compression or both, allowing great flexibility to a system administrator.

Abstract: The capability to encrypt or compress the traffic over network links, thus improving the security of the link on the performance of the links, and the capability to encrypt/decrypt data stored on the storage devices without requiring specialized hosts or storage devices. In a first embodiment, traffic to be routed over a selected link needing encryption and/or compression is routed to hardware which performs the encryption and/or compression and returned for transmission over the link. A complementary unit at the second end of the link routes the received frames to complementary hardware to perform the decryption and/or decompression. The recovered frames are then routed to the target device in a normal fashion. In a variation of this first embodiment the hardware is developed using an FPGA. This allows simple selection of the desired feature or features present in the switch. The switch can be easily configured to perform encryption, compression or both, allowing great flexibility to a system administrator.

Abstract: Managing cluster membership and providing and managing locks in the switches forming the interconnecting network. To manage the cluster membership, a zone is created, with indicated members existing in the zone and the zone being managed by the switches. The nodes communicate their membership events, such as alive messages, using an API to work with the switch to which they are attached. The desired membership algorithm is executed by the switches, preferably in a distributed manner. Each switch then enforces the membership policies, including preventing operations from evicted nodes. This greatly simplifies the programs used on the nodes and unburdens them from many time consuming tasks, thus providing improved cluster performance. In a like manner, the switches in the fabric manage the resource locks. The nodes send their lock requests, such as creation and ownership requests, to the switch to which they are connected using an API.

Abstract: A user (e.g., a network administrator) can enter user verification information once for each switch on which the user desires to perform an administrative activity (e.g., ROM flash, reboot, etc.). Rather than having to enter the user verification information each time a switch is accessed for an administrative activity, the verification information is entered once and stored in non-volatile memory for subsequent use when accessing the switch.

Abstract: A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports.

Abstract: A “high availability” system comprises multiple switches under the control of one more control processors (“CPs”). Each CP performs a staged startup process when failing-over from another CP or otherwise booting up. The staged startup process involves multiple stages of processing of various executable components of the image. Some stages may depend on the prior execution of other stages. The preferred staged startup process includes the use of a staging table which permits the standby image's FSS facility to efficiently schedule the various stages of the fail-over process taking into account the inter-stage dependencies.

Abstract: A “high availability” system comprises multiple switches under the control of a control processor (“CP”). The firmware executing on the processor can be changed when desired. Consistent with the high availability nature of the system (i.e., minimal down time), a single CP system implements a firmware change by loading new firmware onto the system, saving state information pertaining to the old firmware, preventing the old firmware from communicating with the switches, bringing the new firmware to an active state and applying the saved state information to the new firmware.

Abstract: A “high availability” system comprises multiple switches under the control of a control processor (“CP”). The firmware executing on the processor can be changed when desired. Consistent with the high availability nature of the system (i.e., minimal down time), a single CP system implements a firmware change by loading new firmware onto the system, saving state information pertaining to the old firmware using a reboot manager as a standby image, preventing the old firmware from communicating with the switches, bringing the new firmware to an active state and synchronizing the saved state information to the new firmware using the reboot manager as an active image.

Abstract: A “high availability” system comprises multiple switches under the control of multiple control processors (“CPs”). One of the CPs is “active,” while the other CP is in a “standby” mode. Upon detection of a failure of the active CP, fail-over occurs to the standby CP. The standby CP re-issues all messages that the previously active CP had issued and which had not yet completed when the fail-over occurred. The newly active CP uses a different range of transaction identifiers (“XIDs”) than its predecessor CP. By using a different range of XID values, the newly active CP determines whether an incoming response message is responsive to a message that originated from the previously active CP or the newly activated CP. The currently active CP ignores all response messages that do not have an XID in its range, thereby ensuring proper and reliable messaging.

Abstract: A device for converting between the trunked and untrunked transmission of Fibre Channel frame data and for providing connections using longer distance links is described. During conversion, the device manages the flow of frame data in both the egress (from Fibre Channel ports to a non-Fibre Channel port) and ingress (from a non-Fibre Channel port to Fibre Channel ports) directions. In the egress direction, the device operates as a FIFO to transmit all frames received from the Fibre Channel ports to the non-Fibre Channel ports. In the ingress direction, every frame received by the non-Fibre Channel port is stored in one of up to four storage segments based on the frame data's virtual circuit and path number identifiers. Frames are transmitted out of each storage segment in the order in which they are received therein. The device may be a stand-alone device. The device may also be incorporated into a Fibre Channel switch or other apparatus that connects to a Fibre Channel network or switch.

Abstract: The invention relates to graphical user interfaces for managing electronic networks, such computer networks, storage area networks (SANs), and the like. Specifically, the invention provides a simplified means of managing large numbers of parameters associated with devices in such networks. In a preferred embodiment, the invention provides a method of displaying devices forming a network. In a first step, a computer system associated with a graphical user interface queries the network to determine what devices are present in the network, and the interconnections of such devices. The results of this determination are stored, as is the time of this determination. Later, a second query is performed and the results are compared to the first query. Symbols representing elements of the network are displayed on the graphical user interface.

Abstract: A method of routing traffic in a switch includes forming an optimized routing table specifying for each switch ingress port an exit port to be utilized to reach a specified destination domain. The optimized routing table is formed in accordance with load distribution, oversubscription, and fragmentation criteria. The optimized routing table is distributed to a set of ingress ports of the switch.

Abstract: A load balancing technique for use in a switch fabric balances network traffic from a plurality of end node devices based on the volume of traffic on the peripheral links, not simply the rated bandwidth of the peripheral links. In one embodiment, weight values, based on the volume of peripheral link traffic, are used to modify default cost values associated with the peripheral links. The modified default cost values are then used in the load balancing process. In another embodiment, the costs of the peripheral links are adjusted commensurate with the volume of peripheral link traffic.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: A switch having a higher speed port, one or more slower speed ports, a larger buffer memory and numerous larger counters to achieve higher speed and longer range of communication. In one embodiment a larger switch having a larger buffer memory and larger counters connects to a smaller switch having a smaller buffer memory and smaller counters, the larger switch practically expanding the buffer memory and counters in the smaller switch. A combination of several counters can also avoid buffer overrun in any switches in the frame flow path due to the mismatch between the counter capabilities, the limitations of physical buffer spaces or the mismatch between transmission speeds. In another embodiment, the buffer spaces in several switches can be aggregated or cascaded along a frame path so that there are enough credits to maintain a high-speed transmission over a long distance.

Abstract: Placing virtualization agents in the switches which comprise the SAN fabric. Higher level virtualization management functions are provided in an external management server. Conventional HBAs can be utilized in the hosts and storage units. In a first embodiment, a series of HBAs are provided in the switch unit. The HBAs connect to bridge chips and memory controllers to place the frame information in dedicated memory. Routine translation of known destinations is done by the HBA, based on a virtualization table provided by a virtualization CPU. If a frame is not in the table, it is provided to the dedicated RAM. Analysis and manipulation of the frame headers is then done by the CPU, with a new entry being made in the HBA table and the modified frames then redirected by the HBA into the fabric. This can be done in either a standalone switch environment or in combination with other switching components located in a director level switch.

Abstract: A network comprises a plurality of interconnected switches that implement a topology database synchronization technique in which each switch determines whether its topology database has already been transmitted to a neighboring switch when a new link is formed to the neighboring switch. When a new electrical connection is detected, the local switch determines whether any of its other ports have already been connected to the same neighboring switch. If no other port on the local switch has been connected to the neighboring switch, the local switch transmits its topology database to the neighboring switch. If the local switch determines that it has already been connected to the neighboring switch via another one of its ports, the local switch does not yet again copy of the database to the neighboring switch. Also, link state record updates are propagated via only one inter-switch link to a neighboring switch, not all possible links.

Abstract: A network of switches that employ Registered State Change Notifications (RSCNs) with enhanced payloads is disclosed. In one embodiment, the network comprises multiple switches coupled together, and multiple node devices each directly-coupled to at least one other switch. Each of the switches preferably provides RSCNs to other switches when a node device state change is detected. One or more of the RSCNs preferably includes a device entry having more than four properties associated with the node device undergoing the state change. The switches receiving the enhanced RSCNs preferably maintain caches of remote node device entries copied from the RSCN device entries. The device entries preferably include one or more of the following: Owner Identifier, Port Type, Port Identifier, Port Name, Node Name, Initial Process Associator, Node IP Address, Class of Service, FC-4 Types, Port IP Address, Fabric Port Name, and Hard Address. Traffic overhead may advantageously be reduced.

Abstract: An Infiniband (IB) router with an internal subnet architecture is disclosed. It comprises multiple port interface circuits interconnected by an internal IB subnet. The multiple port interface circuits each connect to an external IB subnet and preferably determine new local route headers (LRH) for global IB packets (i.e. packets having a global route header (GRH)). The new LRHs for externally received packets include a destination local identifier (DLID) value that identifies another port interface circuit in the router, whereas the new LRHs for internally received packets include a DLID value that identifies an end node or router in the external subnet to which the port interface circuit is attached. The internal IB subnet transports IB packets between the port interface circuits, directing them according to the contents of the LRHs. The internal subnet may take the form of an IB switch or a network of IB switches.