Patents Assigned to BTA Technology Inc.
  • Patent number: 6304097
    Abstract: A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: October 16, 2001
    Assignee: BTA Technology, Inc.
    Inventor: James C. Chen
  • Patent number: 6300765
    Abstract: A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: October 9, 2001
    Assignee: BTA Technology, Inc.
    Inventor: James C. Chen
  • Patent number: 6278964
    Abstract: An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 21, 2001
    Assignees: Matsushita Electric Industrial Co., Ltd., BTA Technology Inc.
    Inventors: Jingkun Fang, Hirokazu Yonezawa, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu
  • Publication number: 20010000948
    Abstract: A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect.
    Type: Application
    Filed: January 8, 2001
    Publication date: May 10, 2001
    Applicant: BTA TECHNOLOGY, INC.
    Inventor: James C. Chen
  • Patent number: 5790436
    Abstract: A system and method of simulating operation of an integrated circuit. First, circuit characteristics of circuit components are measured, and a set of circuit simulation model parameters are generated for each measured circuit component. Then, the operation of predefined circuit primitives is simulated using each of the generated sets of circuit simulation model parameters. The circuit primitives include the measured circuit components. The simulated operations are then analyzed to select ones of the simulated operations that are worst, best and nominal with respect to a specified circuit performance parameter and to extract model parameters corresponding to the worst case, best case and nominal case sets of circuit simulation model parameters from the generated sets of circuit simulation model parameters. Each extracted set of circuit simulation model parameters comprises one of the generated sets of circuit simulation model parameters.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: August 4, 1998
    Assignee: BTA Technology, Inc.
    Inventors: James Chieh-Tsung Chen, Zhihong Liu, Chenming Hu, Ping Keung Ko