Abstract: Computer system comprising a communication bus, a plurality of units connected to the bus, in which the bus includes a plurality of bus segments, each bus segment being concatenated with at least one adjacent bus portion by means of buffer registers to transfer a data item from the adjacent bus segment to the bus portion, the computer system further comprising an arbitration unit to control, for each bus segment, the simultaneous access to the different segments, in a mutually exclusive way, by the units connected to each of the segments and by the buffers for concatenation of each of the segments with at least one adjacent segment.

Abstract: A data-processing system with cc-NUMA architecture including a plurality of nodes each constituted by at least one processor intercommunicating with a DRAM-technology local memory using a local bus, the nodes intercommunicating using remote interface bridges and at least one intercommunication ring. The at least one processor has access to a system memory space defined by memory addresses.

Abstract: A slave device, connected directly to a system bus, which system bus requests the execution of a complex communication protocol, is controlled by another device, connected to the system bus, which identifies the slave device as the target of a transaction on the system bus, executes the communication protocol and sends to the slave device through an auxiliary interface a first identification signal, a second signal for instructing execution of the transaction, and receives from the slave device, through the auxiliary interface, a transaction executed signal. In this way the interface logic of the slave device is reduced to the minimum since the slave device is not required to execute the communication protocol.

Abstract: Interface bridge (13) between a system bus (ASBUS) and at least one local bus (11, 12), the system space directly addressable through said system bus being greater than the system space directly addressable through the local bus, comprising a plurality of programmable decoders (17, 18, 19) each of which defines a distinct range within the range directly addressable through the local bus, and a range attribute as range of local bus addresses to be translated or to be transferred directly to the system bus and also identifies a local bus address as being included or otherwise within the range, so that depending on whether the local bus address belongs to one of the ranges or not and on the range attribute, the local bus address is transferred to the system bus as a direct address or as an address translated by a translation logic (20, 21) and capable of addressing the entire system space.

Abstract: Dynamic random access memory with variable configuration depending on the number and capacity of standard memory modules, of DIMM type plugged into a first plurality of slots of a memory motherboard comprising a control unit, into which it is possible to plug, into the first plurality of slots, in substitution for the memory modules, expansion supports, in turn provided with a second plurality of slots for the insertion of standard memory modules of DIMM type, and of column address latch registers each associated with a slot of the second plurality and thereby to support and allow the configurability and operability of interleaved-block memory, and access cycles, with partial time overlap, without renouncing the use of commercially available DIMM memory modules and without burdening the basic memory configuration with all the overheads required to support the interleaved-block configuration.

Abstract: Integrated circuit component with terminals for connection to an external communication channel or bus, serial test interface and a configuration register whose content defines operational modes of the integrated circuit, in which the configuration register is loaded with a default configuration, applied externally, through the serial test interface in the course of an initializing phase in which a reset signal applied to the integrated circuit is asserted and in which the default configuration is modifiable via SW or FW, through the external communication channel when the reset signal is deasserted.

Abstract: In a multiprocessor system with shared resources, which several processors access via a system bus by presenting bus access requests to an arbitration unit and receiving from the latter access grant signals and in which the busy state of a resource or a conflict of consistency determine the generation of a RETRY signal and compel the processor, which has obtained access to the bus, to execute an access RETRY attempt, consecutive repeated access RETRY attempts of the same processor activate logic of the arbitration unit which temporarily mask, for a varying duration, the access requests of the same processor for the execution of further consecutive RETRY attempts, the varying duration first increasing as a function of the number of further RETRY attempts and then varying in a random manner.

Abstract: A memory access limiter for random access dynamic memory of data processing systems formed by several modules which can be independently activated in partial temporal superimposition, each by a memory start command, comprising a bidirectional counter which periodically increments at a constant period defined by a clock signal, by a value representative of the electrical charge delivered by a power supply to an output buffer capacitor and decrements, at each memory start command, by a value representative of the electrical charge drained at each memory operation activated by the memory start command, a predetermined decremented count state of the counter identifying a maximum admissible discharge condition of the buffer capacitor below which it is necessary to inhibit any further activation of the memory until the count state of the counter is no longer below the predetermined count state.

Abstract: In a synchronous arbitration unit with round-robin priority for arbitrating between N requests (Ri) for access to common resources of a multiprocessor system, the requests stored in an input register timed by a clock signal are applied as inputs to a fixed-priority arbitration network having 2N-1 inputs, N-1 of the requests being applied both to a first set of N-1 lower-priority inputs of the network and, through masking circuits which selectively mask the requests with a binary masking configuration generated by mask-generating circuits in accordance with predetermined priority-rotation criteria, to a second set of N-1 higher-priority inputs of the network, in the same order of input priority. The grant signals output by the network are latched in an output register after logical OR of the grant signals associated with the same request and the arbitration unit thus formed has a minimal arbitration time and is constituted by a small number of logic components.

Abstract: A multi-processor system in wherein a plurality of processors have access to a plurality of shared memory modules, comprising a memory control unit, interconnection logic circuits, a system bus for the multipoint connection of the processors to the memory control unit and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus and the memory control unit, whilst the transfer of data to and from the memory modules takes place through data channels which connect the various processors on a point-to-point basis to the interconnection logic circuits and via these to a memory data transfer channel.

Abstract: Resolution transforming raster based imaging system where an image is formed by displaying dots arranged along scan lines, scanned by an energization beam, the scan lines having a predetermined resolution and the system is driven by an image bit map having rows with resolution multiple of said predetermined resolution, a subset of the rows being related to the scan lines, bits in rows unrelated to scan lines, and representative of dots to the displayed being displayed as dots offset to a next adjacent scan line and with a size related to the surrounding bit pattern.

Abstract: In a power supply with a boost pre-regulator and power factor correction devices the voltage induced in an auxiliary winding magnetically coupled to the inductor of the pre-regulator and rectified by a diode bridge charges an integrating capacitor, shunted by a discharging resistor, to a voltage which compared with predetermined reference voltages allows to detect and to signal anomalous operative conditions, such as overload or unoperativeness of the power factor correction devices for the execution of suitable intervention procedures.

Abstract: An endless ink ribbon cartridge with protected splice of the endless ribbon, wherein a reactance detector element housed in the cartridge at a location close to a predetermined travel path of the ink ribbon increases its reactance as a conductive strip disposed on the ribbon at a predetermined location relative to the splice moves close past the detector element, the reactance increase being detected by a protection arrangement external of the cartridge to prevent printing operations from being carried out through said splice.

Abstract: A computer frame of riveted modular construction, formed by a plurality of essentially flat structural members provided with stiffening ribs which members are formed from zinc plated sheet metal and only joined together by riveting following an additional step of fully zinc plating the individual members, with no need for any further protective and finishing treatments.

Abstract: Printer with multifunctional paper handling capability having a lambda rear front structure section, a first (P1) paper path for paper front feeding by a first removable tractor set (21), a second paper path (P2) for cut sheet frontal feeding by driving rollers (22) and a third paper path (P3) for paper rear feeding by the first tractor set or a second tractor set (41), all the manual paper loading operations being performable from the printer front having a dihedral recess.

Abstract: Digital information error correcting apparatus for the correction of single errors (SEC), the detection of double errors (DED) and multiple single byte errors (SBD) and the correction of an odd number of single byte errors (ODDSBC) comprising a syndrome generator with generation matrices constituted by the juxtaposition of a plurality of non-zero and distinct submatrices having b rows and r columns where b is the number of bits per byte and r (r.gtoreq.b+2) is the number of syndrome and error check bits, each constituted by an identity submatrix Ib having b rows and columns, vertically aligned over a matrix H having r-b rows and b columns formed by an even number .gtoreq.2 of rows of all 1 elements and the remaining rows being all 0 elements.

Abstract: A method and associated apparatus for enhancing the display or print of greys in a two-tone digitized image consisting of storing a portion of a binary image map including a central bit under examination to be displayed and in testing if the said central bit is representative of an isolated dot or whether in a region around the said central bit in one of a plurality of predetermined directions there is an isolated dot at a predetermined distance from the said central bit, to display the central bit as a dot of reduced dimensions in such a way as to convert the display of an isolated dot in the display into a plurality of smaller dots with aggregate areas equivalent to the isolated dot and distributed around the location of the isolated dot identified from the image map.

Abstract: An electrophotographic apparatus incorporating a sorter device formed by a double pair of driving rollers for ejecting sheets from the apparatus and delivering them into a collecting bin, the two roller pairs acting on the side edges of the sheets at selectively controllable velocities to selectively produce an angular deflection of the outgoing sheets in either of two directions and their delivery into the collecting bin in different positions rotated from each other, the bin having an opening dihedral with side walls which define the maximum amounts of imparted deflection for the two positions.

Abstract: A wire printhead comprising a plurality of electromagnets and a corresponding plurality of armatures, each provided with an actuator arm forming, with the juxtaposed armature to an electromagnet, a lever of first order for actuating an impression wire attached to a free end of the actuator arm, said lever being biased to the rest position by a flexurally pre-loaded leaf spring acting on the lever in a predetermined position with respect to the lever fulcrum, through a resilient element which defines the point of application to the lever of the force from the leaf spring.

Abstract: Serial printer having a printing support conveying lid formed by a rigid plate hinged to the printer and extending for the whole lenght of the print line the plate being provided with a resilient lip having a free edge located immediately dowstream of the print line, spaced apart from a platen for a rest position of the lid and in contact with the platen for an active position of the lid, the lid being held in rest position by resilient bias means and driven in working position by the interference with the lid of pressure pads steady with the printing head slidable along the print line, when the printing head is located along the print line in a position other than a travel end position, in which interference does not occurr.