Abstract: Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

Abstract: A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips. The microprocessor includes an addressable non-volatile memory for storing information including a number of key values and program instruction information. Each chip's memory is organized into a number of blocks, each block including a number of rows of byte locations. Each row of each block further includes a lock bit location, the total number of which provide storage for a lock value uniquely coded to utilize a predetermined characteristic of the memory to ensure data protection. Each memory chip is constructed to include security control logic circuits which include a security access control unit and a volatile access control memory containing a plurality of access control storage elements.

Abstract: In a data processing system, a measurement of the cumulative time used in the performance of an intermittent activity can be required. To determine this cumulative time, a memory location is designated during initialization that is to contain the value of the system clock determined at each initiation of the intermittent activity. A second memory location is provided during initialization that is to contain the accumulated total of the measurements taken to perform the intermittent activity. At each termination of the intermittent activity, the contents of the first and second locations are retrieved from the main memory. The value stored in the first main memory location is then subtracted from the system clock value at the termination of the current intermittent activity and the resulting value is added to the contents of the second location. The resulting value of the addition operation is then stored in the second main memory location.

Abstract: In a data processing system using a virtual memory addressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value. This invention minimizes the amount of logic required to back out of a software instruction after execution has begun and is faster than checking if all resources are present before any state change is made during the execution of a software instruction.