Abstract: A monolithic digital-to-analog converter integrated circuit is disclosed including a first plurality of more significant bit switches having scaled bit switch currents and including a second plurality of lesser significant bit switches, the output nodes of which are coupled to a ladder network which contributes a binary-weighted portion of each lesser significant bit switch current to the summed analog output current. First and second output conductors, separate and apart from one another, are used to couple the output nodes of the more significant bit switches and the output current of the ladder network, respectively, to the analog output current pad. First and second ground voltage pads are included for isolating waste current conducted by the more significant bit switches from currents returned by the ladder network to the ground voltage. The waste current nodes of the lesser significant bit switches are conducted to the same ground voltage pad that conducts the currents returned by the ladder network.

Abstract: A bar code reading system having a wand that detects variations in light reflected by bars and spaces of the label produces a sequence of corresponding pulses and intervals as the wand scans the label. The entire sequence of pulses and intervals is input to a microprocessor system which produces corresponding digital duration numbers. The microprocessor system computes a reference number for a first character of the label and compares each digital duration number of the character to the reference number to compute a binary number with bits that are a "one" or a "zero" according to whether corresponding digital internal numbers exceed or are less than the reference number. If the number of "ones" in the binary number is too low or too high, the microprocessor decreases or increases the reference time, compares the digital duration number with the adjusted reference number, and re-determines if the resulting value of the binary number has the correct number of "ones".

Abstract: Means and method is disclosed for achieving a low profile optical coupling to a module comprising an optoelectronic device together with other circuitry. Maintaining the optoelectronic device parallel to the substrate on which it and the associated circuitry are mounted enables the use of standard, well known manufacturing assembly techniques while providing electrical connection to the electric ports of said optoelectronic device. Subsequent to the electrical interconnection operation, the optoelectronic device is moved, together with its connections, to a position substantially orthogonal with the mounting substrate. Optical fiber, light coupling is utilized. The low profile of the overall module package is achieved by introducing the optical fiber in a direction generally parallel with the substrate and perpendicular to the light active surface of the optic port of the optoelectronic device.

Abstract: A digital-to-analog converter circuit includes an open-loop reference circuit for regulating a plurality of bit switch currents and utilizes a high-speed single-ended input interface network for level shifting digital input signals to the bit switches whereat the level shifted input signals switch against a substantially fixed threshold voltage. The single-ended input interface network includes a PNP input transistor coupled to an input terminal and coupled by a resistor to a regulated voltage. The PNP input transistor is coupled to a level shifting network including an emitter follower transistor and a zener junction biased by a current source. The threshold voltage is also developed by a level shifting network that includes a zener junction for compensating variations within the level shifting network of the single-ended input interface network.

Abstract: An open-loop voltage reference circuit, adapted to regulate a plurality of bit switch currents within a digital-to-analog converter, includes a zener diode reference leg for developing a reference voltage. The reference leg also includes a base-emitter junction voltage multiplier for creating a compensating voltage having a temperature tracking coefficient that is equal and opposite to that of the zener diode junction voltage. The reference voltage developed by the reference leg is used to bias a temperature independent current within a slave leg, and a current mirror circuit mirrors the current within the slave leg for supplying a constant current to the reference leg. The magnitude of the reference voltage is reduced through a divider leg, and an emitter follower leg provides a low impedance bias voltage for driving the plurality of bit switch current sources.

Abstract: Apparatus for compensating thermal drift of temperature sensitive circuitry in an integrated circuit by heating the temperature sensitive circuitry by applying power to a heating element in the integrated circuit, testing the temperature sensitive circuitry, and trimming a thin film resistor in accordance with the testing results. The heating element is an integrated resistor adjacent to or surrounding the temperature sensitive circuitry. The integrated circuit further includes a thin film compensating resistor which affects or determines the degree of temperature sensitivity of the temperature sensitive circuitry. As the temperature of the temperature sensitive circuitry is increased, testing apparatus is utilized to measure a temperature sensitive parameter of the temperature sensitive circuitry.

Abstract: An isolation amplifier includes an electrically floating comparator having inputs coupled to inputs of the isolation amplifier. Operating power is supplied to the isolation amplifier by an electrically floating rectifier circuit. A triangular waveform generator produces a triangular output signal which is combined by means of a first coupling capacitor with a differential input signal applied to the inputs of the isolation amplifier. A second coupling capacitor couples the triangular waveform to the floating rectifier circuit. The floating comparator circuit produces a pulse width modulated output signal representative of the magnitude of the differential input signal. A demodulator circuit inverts the pulse width modulated signal to an analog output signal which is an amplified replica of the differential input signal. The analog output signal is electrically isolated from the differential input signal.

Abstract: Apparatus and method for compensating thermal drift of temperature sensitive circuitry in an integrated circuit by heating the temperature sensitive circuitry by applying power to a heating element in the integrated circuit, testing the temperature sensitive circuitry, and trimming a thin film resistor in accordance with the testing results. The heating element is an integrated resistor adjacent to or surrounding the temperature sensitive circuitry. The integrated circuit further includes a thin film compensation resistor which affects or determines the degree of temperature sensitivity of the temperature sensitive circuitry. As the temperature of the temperature sensitive circuitry is increased, testing apparatus is utilized to measure a temperature sensitive parameter of the temperature sensitive circuitry.

Abstract: A system for linearizing non-linear transducer output signals includes an analog-to-digital converter having a plurality of digital outputs. A first group of the most significant bits of the analog-to-digital converter digital outputs are coupled to address inputs of a read only memory. The remaining digital outputs of the analog-to-digital converter are coupled to a first group of inputs of a digital multiplying circuit. A first group of data outputs of the read only memory are coupled to a first group of inputs of a summing circuit and represent intersection points of a piece-wise linear approximation to a mathematical curve representing the relationship between unlinearized data produced by the analog-to-digital converter and linearized data produced by the linearizing system. A second group of the read only memory data outputs are coupled to a second group of inputs of the digital multiplying circuit and represent the slopes of straight lines extending from one intersection point toward another.

Abstract: A digital to analog conversion system includes a memory for storing a plurality of correction codes corresponding to corrections required to compensate for inaccuracy in output currents of a main digital to analog converter (DAC) contained in the digital to analog conversion system. A plurality of the logic inputs applied to the inputs of the main DAC are also applied to the address inputs of the memory. A trim DAC having its inputs coupled to the data outputs of the memory converts the correction code stored in the addressed location of the memory into a correction current which is utilized externally of the main DAC to modify the net amount of output current available from the main DAC to compensate for inaccuracy of the unmodified output current. An output signal from a temperature sensor is connected to a digital number which is also applied to a plurality of the address inputs.

Abstract: A transducer bridge amplifier system includes a first operational amplifier having positive and negative inputs connected, respectively, to first and second output nodes of the bridge. The output of the operational amplifier is connected to a third node of the transducer bridge. A transducer of the transducer bridge is connected between the second node and the third node. A second operational amplifier has its positive input connected to ground and its negative input connected to the first node. A feedback resistor is coupled between the output of the second amplifier and a negative input of the second amplifier. An output signal produced by the second operational amplifier has a linear response to transducer deviation and low sensitivity to offset voltages of the first and second operational amplifiers.

Abstract: A system for automatically calibrating a main digital to analog converter (DAC) includes first and second adjustment DAC's, an offset DAC, a difference amplifier, an analog to digital converter (ADC), a microprocessor, and an analog switch. To calibrate the offset of the main DAC, the microprocessor causes "zeros" to be applied to the digital inputs of the main DAC and the offset DAC. The output of the offset DAC is coupled to an input of the difference amplifier. The microprocessor causes a ground voltage to be applied to the second input of the difference amplifier via the analog switch. The output of the difference amplifier is inputted to the ADC, which produces a first word. The first word is stored by the microprocessor. The analog switch is activated to apply the analog output voltage of the main DAC to the second input of the difference amplifier. The ADC produces a second word which is compared to the first word.

Abstract: A switching regulator system and method for producing regulated output voltage and current in response to an unregulated input voltage, including a plurality of switching regulators connected in parallel and control circuitry to accomplish uniform loading of each of the switching regulators according to the rated current producing capacity of each regulator. The switching regulators each include a switching transistor, an inductor responsive to the switching transistor, a free-wheeling diode responsive to the inductor, and a comparator for providing an output signal representative of whether the regulated output voltage exceeds a threshold. The control circuitry poroduces a control signal repesentative of the logical OR of the comparator output signals.

Abstract: This relates to a packaging apparatus for coupling modular hardware (e.g. printed circuit boards) to both the bus of a digital system and to industrial end devices such as relays, thermocouples, etc. A motherboard connected to the rear of a card cage couples a first group of edge connectors on each card to the digital system bus. The motherboard has a plurality of clearance holes therein for providing access to a second group of edge connectors on each card. A dedicated terminal assembly having end device field wiring connected thereto is electrically coupled to the second group of edge connectors of a particular card by either passing a suitable connector attached to the assembly through one of the clearance holes or by coupling the second group to the assembly by a suitable cable which passes through the hole.

Abstract: A method for processing a semiconductor wafer to reduce electrical noise, to reduce the surface component of junction leakage current, to increase junction reverse breakdown voltage, and to increase field inversion voltage. Subsequent to last high temperature processing to which the semiconductor wafer is exposed in course of its manufacture, the semiconductor wafer is subjected to an annealing cycle in an inert ambient at a temperature in the range of 600 to 950 degrees Centigrade. At this point the semiconductor wafer has a field oxide thereon produced by prior processing operations. The annealing cycle stabilizes the semiconductor device by allowing an oxide-semiconductor interface region of the wafer to attain a minimum energy configuration, thereby reducing the surface-state charge density. The semiconductor wafer is then exposed to an oxidizing ambient for a short time to increase the oxide charge.

Abstract: This relates to a transformer coupled isolation amplifier employing multiple primary and secondary windings to separate power supply currents from signal currents. An input section includes an input amplifier, a flyback modulator and a first flyback demodulator. An output section includes an output amplifier and a second flyback demodulator. A power section alternately provides a voltage and a high impedance to the transformer, which voltage is coupled to the input and output amplifiers via first and second primary and first and second secondary windings respectively for the purpose of providing positive and negative power sources to the amplifiers. The input demodulator is coupled to the output demodulator by third primary and secondary windings.

Abstract: A semiconductor interface circuit and method of operation for transmitting and receiving information between a telephone set and a four wire switching system. The interface circuit includes DC current sources which may be modulated by a voice signal from the switching system. The current sources provide both DC power and the voice signal to the telephone set through a two wire cable. A high impedance amplifier amplifies the signal on the cable, which cable signal includes a DC voltage, a microphone signal from the telephone set, and a component due to the voice signal from the switching system, all three being dependent on the cable length. Cable termination resistors are optional. The signal from the switching system and the DC component of the output signal of the amplifier are multiplied by an inverting multiplier circuit.

Abstract: A complementary transistor output circuit and method incorporates an optical coupler including a light emitting diode and a phototransistor connected between the base electrodes of a complementary pair of output transistors including a PNP transistor and an NPN transistor. The emitter of each of the output transistors is connected to an output of the output circuit. The base electrodes of the PNP output transistor and the NPN output transistor are connected, respectively, to first and second current source circuits. The collector electrode of the NPN output transistor is coupled by means of a first feedback circuit including a first resistor and a PNP transistor to the anode of a light emitting diode. The collector electrode of the PNP output transistor is coupled by means of a second feedback circuit to include a second resistor and an NPN transistor to the cathode of the light emitting diode.

Abstract: An optical coupling system is described incorporating a light emitting semiconductive device mounted on a substrate having an electrically conductive strip leading to and from the device. A plurality of photo detector, semiconductive devices are mounted on the substrate adjacent to and co-planar with the light emitting device. A housing is mounted over the semiconductive devices and is filled with a clear light transmitting resin; the interior surfaces of the housing are light reflecting so that light emitted by the light emitting semiconductive device is reflected and diffused therefrom impinging upon each of the photo detector, semiconductive devices.

Abstract: A ceramic substrate is provided with a plurality of planar conductors formed on a surface of the substrate; conductors extend substantially radially from an imaginary point on the surface of the substrate. A layer of dielectric material is formed over the major portion of each of the conductors to form a ring of dielectric material to which a ferrite toroidal core is adhesively secured. The core is precoated with an insulating material prior to adhesively being secured to the dielectric ring. A plurality of wire conductors are wire bonded at each end thereof to the exposed ends of the metal conductors on the substrate.