Abstract: An example system includes a processor to monitor activity on a database server to generate an events stream. The processor can convert the events stream into a time series that approximates activity load at the database server using an exponential smoothing. The processor can also send the time series to a streaming analytics engine.

Abstract: A method for curing antenna violations on an integrated circuit that includes multiple levels includes: obtaining a design of a circuit, the design including a first element connected to first device and a second element connected to one or more second devices, wherein the first and second elements both receive a common signal; determining that an antenna violation exists in on the first element at a first level of the multiple levels; and modifying the design of the circuit to add a connected between the first element and the second element at the first layer or at a layer below the first layer.

Abstract: Mechanisms are provided for implementing a generative adversarial network (GAN) based restoration system. A first neural network of a generator of the GAN based restoration system is trained to generate an artificial audio spectrogram having a target damage characteristic based on an input audio spectrogram and a target damage vector. An original audio recording spectrogram is input to the trained generator, where the original audio recording spectrogram corresponds to an original audio recording and an input target damage vector. The trained generator processes the original audio recording spectrogram to generate an artificial audio recording spectrogram having a level of damage corresponding to the input target damage vector. A spectrogram inversion module converts the artificial audio recording spectrogram to an artificial audio recording waveform output.

Abstract: A computer receives a request to verify a location of a primary device. The computer receives an Indicated Primary Device Location “IPDL”. The computer shows within a display a dynamically located virtual representation of a predetermined Astronomical Reference Object “ARO”. The virtual representation indicates a real-time offset between a Display Reference Indicator “DRI” and the ARO. The computer receives primary device orientation metadata from sensors associated with the primary device and generates a Measured Primary Device Orientation “MPDO” when the device is in a location verification orientation. The computer calculates an Expected Device Orientation “EDO” for a reference device arranged in the PDVP while at the IPDL. The computer generates a Location Verification Value “LVV” based, at least in part, on comparing the MPDO and the EDO. When the computer determines the LVV exceeds a predetermined verification threshold, providing an indication that the indicated primary device location is verified.

Abstract: A cold plate apparatus includes walls that surround an active volume adjacent to an inlet plenum; the walls include an inlet opening at one end of a top side of the inlet plenum and a plenum opening between the inlet plenum and the active volume. Also included is a blocker that partially separates the inlet plenum from the active volume. The blocker is structurally configured to preferentially redirect flow from the inlet plenum into the active volume.

Abstract: A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.

Abstract: A method, system, and computer program product for recommending an initial database security model. The method may include identifying a plurality of nodes connected to a security network. The method may also include analyzing security characteristics of each node of the plurality of nodes. The method may also include identifying, from the security characteristics, key factors for each node. The method may also include calculating similarities between each node of the plurality of nodes. The method may also include building a self-organized centerless network across the plurality of nodes by grouping nodes with high similarities based on the similarities between each node, where the self-organized centerless network is a centerless network without a central management server, and includes groups of nodes from the plurality of nodes. The method may also include generating federated security models for the groups of nodes.

Abstract: A method for manufacturing a phase-change memory device includes providing a substrate including a plurality of bottom electrodes, patterning the substrate to form a plurality of pores in the substrate extending from a surface of the substrate to the bottom electrodes, depositing a phase-change material over the substrate, implanting one or more of a Ge, Sb and Te in the phase-change material to amorphize at least a portion of the phase-change material inside the pore, planarizing the device to exposed the surface of the substrate, and forming a plurality of top electrodes over the pores, in contact with the phase-change material.

Abstract: Visual data transmission by an air-gapped system, including: transmitting, by an air-gapped system comprising at least one first computing device, a visual encoding of data via a display; detecting, during capture of the visual encoding of the data by a second computing device via a camera, an error; generating, by the second computing device in response to the error, and alert; and retransmitting, in response to a user input to the air-gapped system, at least a portion of the visual encoding of the data via the display.

Abstract: A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input.

Abstract: A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.

Abstract: A hybrid classical-quantum computing device to execute a quantum circuit corresponding to a variational problem, is configured. The configuring further comprises causing the hybrid classical-quantum computing device to execute the quantum circuit by performing an adiabatic progression operation, wherein the adiabatic progression operation comprises increasing the difficulty of the variational problem from a simplified version of the problem to the variational problem.

Abstract: Embodiments of present invention provide a resistive random-access memory (RRAM) cell. The RRAM cell includes a bottom electrode; a metal oxide layer, the metal oxide layer having a central portion that is in direct contact with the bottom electrode, a peripheral portion that is nonplanar with the central portion, and a vertical portion between the central portion and the peripheral portion; and a top electrode directly above the metal oxide layer. A method of manufacturing the RRAM cell is also provided.

Abstract: An example operation may include one or more of storing a full-step hash of a data file and a reduced-step hash of the data file within a data block of a hash-linked chain of blocks of a blockchain, receiving a request from a client application to verify the data file, determining whether to provide the full-step hash of the data file or the reduced-step hash of the data file based on the request, and in response to determining to provide the reduced-hash, transmitting the reduced-step hash of the data file to the client application.

Abstract: Embodiments are directed to short and/or near short etch rework. A microfluidic device is positioned on a portion of a circuit having a defect. The microfluidic device is caused to dispense etchant that removes the defect of the circuit, where a flow of the etchant is controlled to access the portion of the circuit having the defect to thereby etch away the defect, the flow of the etchant being obstructed from accessing other portions of the circuit. The microfluidic device is used to extract the etchant from the portion of the circuit such that the etchant avoids contact with the other portions of the circuit. The microfluidic device is removed from the circuit.

Abstract: A semiconductor structure includes a power rail contact at least partially disposed between a first source/drain region of a first vertical fin structure and a second source/drain region of a second vertical fin structure. The power rail contact is in contact with a buried power rail disposed under the first and second vertical fin structures. The power rail contact is in contact with at least one of the first and second source/drain regions. A contact cap is disposed above the power rail contact.

Abstract: A semiconductor structure includes a first electrode; a second electrode; a dielectric material between the first electrode and the second electrode, the dielectric material having at least one wall extending from the first electrode to the second electrode to define a void within the dielectric material and between the first electrode and the second electrode; and a layer of phase change material on the at least one wall of the dielectric material and in contact with the first electrode and the second electrode.

Abstract: A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Abstract: A forksheet transistor device includes a dual dielectric pillar that includes a first dielectric and a second dielectric that is different from the first dielectric. The dual dielectric pillar physically separates pFET elements from nFET elements. For example, the first dielectric physically separates a pFET gate from a nFET gate while the second dielectric physically separates a pFET source/drain region from a nFET source drain region. When it is advantageous to electrically connect the pFET gate and the nFET gate, the first dielectric may be etched selective to the second dielectric to form a gate connector trench within the dual dielectric pillar. Subsequently, an electrically conductive gate connector strap may be formed within the gate connector trench to electrically connect the pFET gate and the nFET gate.

Abstract: An embodiment includes classifying an incoming communication message as having an instruction classification based on a natural language processing (NLP) analysis of the incoming communication message. The embodiment extracts, responsive to classifying the incoming communication message as having the instruction classification, user operations as a workflow dataset. The embodiment clusters the workflow dataset into a task cluster with other similar workflow datasets representative of previously-extracted user operations. The embodiment designates the instruction classification as a trigger event based at least in part on the NLP analysis of the incoming communication message. The embodiment generates a robotic process automation (RPA) bot script that comprises program instructions executable by a processor to cause the processor to perform operations that automate the user operations in response to the trigger event.