Abstract: A parallel distributed sample scrambling and descrambling system for fixed-sized packet transmission comprising a parallel scrambler and a parallel descrambler. The scrambler includes; a parallel shift register generator 61 for generating parallel sequences; a sampling means 62 for generating samples from said parallel shift register generator 61; a parallel scrambling means 63 for performing parallel scrambling function by modulo-2 adding the parallel sequences to parallel input data sequences; and a multiplexing means 64.

Abstract: A distributed sample scrambling system comprising scrambler and a descrambler. The scrambler includes a first shift register generator (SRG) 2 for generating scrambler SRG sequence, an exclusive OR gate 7 for generating a scrambled bitstream by adding the binary sequence to a scrambler input bitstream, and first sampling unit 2 for sampling the scrambler SRG sequence at non-uniform sampling intervals.

Abstract: A parallel scrambling system comprises an M-bit (M>1) interleaved parallel scrambler for parallel scrambling input signals and an M-bit interleaved multiplexer for multiplexing output signals from the M-bit interleaved parallel scrambler. With this arrangement, an M-bit interleaved parallel scrambling of input signals is carried out prior to a multiplexing thereof. The parallel scrambling system also comprises an M-bit interleaved demultiplexer for receiving a parallel scrambled and multiplexed signal from the M-bit interleaved multiplexer and demultiplexing it and an M-bit interleaved parallel descrambler for descrambling output signals from the demultiplexer to make original signals recover. As the scrambling of input signals is carried out prior to the multiplexing thereof, the scrambler can be operated at the rate identical to the transmission rate of input signals, thereby reducing the manufacture cost and electric power consumption to a minimum.