Abstract: A gate driving device includes an IGBT and a gate drive circuit, which includes a gate resistor and a gate drive unit. The gate of the IGBT is connected to the gate resistor, and the emitter of the IGBT is connected to a low voltage potential. The peak impurity concentration of the collector of the IGBT is equal to or greater than 1×1016 cm?3, and the time constant, which is the product of a gate input capacitance (Cg) of the IGBT and a resistance value of the gate resistor (Rg) is equal to or less than 500 ns. The IGBT is turned ON or OFF by inputting an ON or OFF signal respectively to the gate via the gate resistor. The gate driving device can lower the spike voltage and reduce the turn-off power loss at the same time in an inductive load circuit when the IGBT is turned off.

Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.