Patents Assigned to c/o FUJITSU SEMICONDUCTOR LIMITED
  • Publication number: 20120153448
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 21, 2012
    Applicant: c/o FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Publication number: 20110161691
    Abstract: A semiconductor integrated circuit includes: a plurality of domains each supplied power supply voltage from corresponding one of a plurality of power supply units; and a plurality of operation control units each connected to corresponding one of the plurality of domains and controlling an operational state of the corresponding domain, wherein each of the domain transmits a operation change request to the corresponding operation control unit, the operation change request representing a request for a change of the operational state with a change in current value of the domain, and the operation control unit calculates a current change rate of the domain resulted from the change of operational state upon receiving the operation change request, and transmits a response signal approving the change of operational state to the corresponding domain in case of the current change rate is within a specified value.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 30, 2011
    Applicant: c/o FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masahiro TATSUMI, Takeshi ISHIBASHI, Takashi SHIMADA
  • Publication number: 20110101462
    Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 5, 2011
    Applicant: c/o FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yasunobu TORII