Abstract: Disclosed is an auto volume control method and system for mixing of sound sources. The control method and system mixes the sound sources by controlling signals of the sound sources automatically inputted by a simple control method, such that the signals from a plurality of sound sources are mixed to prevent an overflow phenomenon of the sound sources from occurring.

Abstract: The present invention provides a diagnostic apparatus using a microphone. More specifically, the diagnostic apparatus utilizes a first microphone, a second microphone, a first unit, a controller and second unit. The first microphone is positioned within an engine compartment and the second microphone is positioned within an interior of a vehicle to receive the noise. The second unit records the noise inputted through the first microphone or the second microphone or both and the controller analyzes and diagnoses a vehicle utilizing the noise recorded by the first unit to determine if a failure in the vehicle has occurred. When a vehicle failure is detected by the controller, the second unit then notifies a user of the location of a failed part in the vehicle.

Abstract: Provided is a system for generating an interpolated frame, which includes an image decoding module configured to decode a first frame from an original image information, the first frame being divided into unit images, and an interpolated frame generating module configured to extract a motion information of each of the unit images between the first frame and the second frame, the motion information being written in a second frame of the original image information, and generate the interpolated frame that is to be inserted between the first frame and the second frame by using the first frame and the motion information of each of the unit images.

Abstract: The present invention features a DMB System for reducing scan time, and a method for the same, wherein, the DBM system comprises a DMB receiving unit and a TPEG-only receiving unit, and is able to reducing scan time for total channels by performing a scanning process for total channels together by the DMB receiving unit and the TPEG-only receiving unit, respectively.

Abstract: An apparatus and method for generating still cut frames from video frames that are executed consecutively includes a storage unit for temporarily storing specific ones of the executed video frames in real-time, a display unit for displaying the video frames, and a controller for controlling the storage unit and the display unit in response to an external input signal. When a still cut command signal is input as the external input signal, the controller controls the video frames, are temporarily stored in the storage unit, to be decided and the decided video frames to be displayed through the display unit. When a signal selecting a specific one of the displayed frames is input, the controller generates the selected frame as a still cut frame.

Abstract: The data interface device accesses a memory operating in synchronization with a clock. A board clock and selective data capturing improve the operating rate of a memory interface and time-synchronize data flow from memory to memory controller with a internal clock produced by the memory controller; or time-synchronize data flow from the memory controller with the board clock. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.

Abstract: A digital video coding system is provided that is capable of reducing the load of a CPU (Central Processing Unit) that controls a video coding system for implementing a digital video data compression/decompression standard such as MPEG-1, 2, 4, H.261 or H.263. In a conventional video coding system, the circuit configuration and control method of a variable length encoder are becoming increasingly complex with the development of a video compression/decompression standard. In a conventional system structure, a complex control operation must be carried out, such that there is a problem in that the load of the CPU controlling the video coding system increases. Thus, the video coding technology is provided to reduce the load of the CPU necessary for controlling a VLC (Variable Length Coding) unit.

Abstract: Disclosed is a video-ready Internet telephone which is compatible with a VoIP (Voice over Internet Protocol) telephone providing a voice communication service over the Internet. The video-ready Internet telephone includes a video processing module for converting a digital video signal into an analog video signal by using a communication protocol for video or converting an analog video signal applied thereto into an digital video signal for transmission through the Internet; and a video input/output module operated in cooperation with the video processing module, for receiving an analog video signal from a camera or receiving the converted analog video signal from the video processing module and displaying corresponding analog video data in response to the received analog video signal on a liquid crystal display (LCD).

Abstract: There is provided a H.264 decoding method for fast CAVLC, which searches multiple tables effectively and fast to obtain coefficients for CAVLC blocks within the shortest period of time such that a decoder with excellent efficiency can be designed for low frequency. The H.264 decoding method for fast CAVLC includes: a first step of obtaining the number of ‘0’s including the firstly inputted bit ‘0’ to the bit ‘0’ right before the bit ‘1’ firstly appearing to obtain a row index value; a second step of obtaining a fix index indicating the first bit ‘1’; a third step of obtaining a column index indicating a bit stream other than the row index and fix index; and a fourth step of obtaining a total coefficient and trailing ones T1s corresponding to the row index value and the column index value.

Abstract: Disclosed is a method for initializing an Internet videophone terminal. In accordance with the method, the Internet videophone terminal is initialized using an initial configuration file therefor based on a specific data format, such that an initial setup process between a service provider and an Internet videophone terminal user can be simplified.

Abstract: Disclosed is a data interface device for accessing a memory that operates in synchronization with a clock. A board clock and selective data capturing are used to improve an operating rate of a memory interface and to match a point of time that data outputted from the memory is inputted to a memory controller with a internal clock produced by the memory controller, or to match a point of time that data is outputted from the memory controller with the board clock. The board clock is used to synchronize a point of time that the memory inputs or outputs the data. The internal clock is passed through a sequential path of an output pad of the memory controller, the memory, and an input pad of the memory controller and then re-inputted into the memory controller thereby the feedback clock is generated. The selective data capturing uses a register part for storing data inputted into the memory controller.

Abstract: Disclosed is a multimedia program download system and method of an apparatus equipped with a multimedia processor, which is capable of downloading a mass of multimedia program through a host interface without using a boot ROM. The present invention provides a multimedia program download control system and method including a multimedia processor efficiently used for system configuration of mobile devices or PDAs, which is capable of downloading a multimedia program to drive a system faster than conventional multimedia program download control systems and methods and constructing a board system simply. The multimedia program download control system of an apparatus is equipped with a multimedia processor in which a multimedia program is downloaded from a host processor and is stored in a program area of a SDRAM. The multimedia processor comprises a host interface, a GDMA (General Purpose Direct Memory Access), a CPU and a reset controller.

Abstract: Disclosed is a DAB (Digital Audio Broadcasting) modem interface for receiving multi-channel, which is capable of receiving two channels at once by providing a sub-channel filtering function to the DAB modem interface, and a method of operating the same. The DAB modem interface includes a serial interface for capturing channel data in bit stream data output from the DAB modem, buffer switching means for classifying the channel data captured by the serial interface for each channel and storing the classified channel data in two buffers assigned for each channel, and sub-channel filtering means for performing a sub-channel filtering operation of comparing a channel value acquired from the multimedia processor with a sub-channel ID value acquired in the course of capturing of the channel data, and generating control signals for controlling the serial interface to provide information on two channels to be captured and the buffer switching means to store data into the two buffers.

Abstract: There is provided a H.264 decoding method for fast CAVLC, which searches multiple tables effectively and fast to obtain coefficients for CAVLC blocks within the shortest period of time such that a decoder with excellent efficiency can be designed for low frequency. The H.264 decoding method for fast CAVLC includes: a first step of obtaining the number of ‘0’s including the firstly inputted bit ‘0’ to the bit ‘0’ right before the bit ‘1’ firstly appearing to obtain a row index value; a second step of obtaining a fix index indicating the first bit ‘1’; a third step of obtaining a column index indicating a bit stream other than the row index and fix index; and a fourth step of obtaining a total coefficient and trailing ones T1s corresponding to the row index value and the column index value.

Abstract: The memory control system includes a memory unit, bus master(s), arbiter, and memory controller. The bus masters output bus use request signals, block mode signals, block information, and drive information for data and outputs data corresponding to block/receive read-out data. The arbiter receives request signals and drive information and outputs a master selection signal used to select a bus master to which access is permitted and the drive signal input from the selected bus master. The bus master selection unit receives block mode signals, block information and data corresponding to the bus masters and outputs the block mode signal, block information and bus master data selected according to the master selection signal. The memory controller receives drive information from the arbiter, block mode signal, and block information from the selection unit, and allows data corresponding to respective line block groups to be sequentially-stored in/read out from respective banks.

Abstract: A motion estimation method using adaptive mode decision is disclosed. The method includes a motion vector difference value calculation step of calculating a motion vector difference value using an input motion vector estimation value x component for a current block and an input x offset corresponding to a current SAD. At the MVD Variable Length Coding (VLC) step, the length of a bit string, which is obtained by performing variable-length coding on an MVDx, is calculated. At a motion vector difference value calculation step, a motion vector difference value is calculated using an input motion vector estimation value y component for a current block and an input y offset corresponding to the current SAD. At an MVD VLC step, the length of a bit string, which is obtained by performing variable-length coding on an MVDy, is calculated. Thereafter, the amount of motion vector coding is produced by adding the MVDx and the MVDy.

Abstract: A dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption with use of a selective latching technique includes a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the frequency-dividing mode of the first frequency-dividing circuit.