Abstract: The embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and a related apparatus and method. The instruction retirement unit includes: a reception subunit, configured to receive a completion request signal; an arbitration subunit, configured to send a completion permission signal to an instruction execution unit after determining that instructions to be completed can be completed, and store instruction completion information of the instructions to be completed into instruction buffer table entries in a buffer; and a retirement subunit, configured to perform, based on the instruction completion information stored in each of the instruction buffer table entries, retirement processing on instructions that have already been completed and have not been retired, and delete the instruction completion information of retired instructions from the instruction buffer table entries.

Abstract: The embodiments of the present application provide a processing unit. The processing unit comprises: an instruction fetching unit configured for fusing instruction of vector configuration instruction and vector operation instruction that are adjacent in order to obtain fusion instruction; an instruction decoding unit configured to decode the fusion instruction to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instruction according to the first execution information, modify vector control register, and bypass the value of the modified vector control register to the vector operation unit; the vector operation unit configured to execute the vector operation instruction according to the second execution information and the value of the modified vector control register.

Abstract: The present disclosure provides a data computing system. The data computing system comprises: a memory, a processor and an accelerator, wherein the memory is communicatively coupled to the processor and configured to store data to be computed and a computed result, the data being written by the processor; the processor is communicatively coupled to the accelerator and configured to control the accelerator; and the accelerator is communicatively coupled to the memory and configured to access the memory according to pre-configured control information, implement a computing process to produce the computed result and write the computed result back to the memory. The present disclosure also provides an accelerator and a method performed by an accelerator of a data computing system. The present disclosure can improve the execution efficiency of the processor and reduce the computing overhead of the processor.

Abstract: Embodiments of the present disclosure provides a device for implementing resource index replacement, comprising an instruction scheduling unit configured to receive a first type, resource index from a resource allocating unit and then issue an instruction to an instruction executing unit for execution, to receive a second type resource index from the resource allocating unit, to execute the instruction from the instruction scheduling unit, and to issue a result of the instruction execution and the second type resource index to a result storing unit. The result storing unit comprises a plurality of resource for storing instruction execution results and execution results. The result storing unit is configured to allocate the first type resource index to an instruction entering the instruction scheduling unit and to allocate the second type resource index to an instruction entering the instruction execution unit.

Abstract: Embodiments of the present disclosure provide a protective apparatus for an indirect access memory controller. The apparatus can include: a bus monitoring unit configured to monitor a bus address and detect an operation type of a bus accessing the indirect access memory controller, update a corresponding window register if the operation type is a window register operation, initiate permission authentication if the operation type is a register controlling operation, and perform list entry configuration if the operation type is a permission list configuration operation; a window register unit configured to store operation addresses of different access types; a permission list unit configured to partition a memory space into several virtual memory protection areas, and independently set a access permission attribute for each memory area; and an unauthorized operation processing unit configured to process a subsequent operation performed when a permission violating access occurs.

Abstract: The present disclosure provides an off-chip memory address scrambling apparatus and method for a system on chip. The apparatus includes a true random number generator, a key memory and an on-chip security controller. The on-chip security controller is connected to the true random number generator, the key memory and an off-chip memory respectively and is configured to read or write data in the off-chip memory and perform address scrambling processing on the data.

Abstract: Embodiments of the disclosure provide a method and apparatus for upgrading a system version of a system. The method can include: acquiring, using circuitry, from a first storage space a current system version identification corresponding to a current system version; acquiring, using circuitry, from a second storage space a backup system version identification corresponding to a backup system version; comparing, using circuitry, the current system version identification with the backup system version identification; and configuring the system based on the comparison.

Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Abstract: Embodiments of the disclosure provide a method and apparatus for encrypting and decrypting data. The method for encrypting data in a computer system can include: receiving, by a memory operation module, a first data and a second data for encryption; determining at least one storage area for a first encrypted data corresponding to the first data and a second encrypted data corresponding to the second data; generating at least one key based on the first and second data and the at least one storage area; and encrypting the first data and the second data using the at least one key to generate the first encrypted data and the second encrypted, respectively.

Abstract: The present disclosure provides a method and a system of verifying access by a multi-core interconnect to an L2 cache in order to solve problems of delays and difficulties in locating errors and generating check expectation results. A consistency transmission monitoring circuitry detects, in real time, interactions among a multi-core interconnects system, all single-core processors, an L2 cache and a primary memory, and sends collected transmission information to an L2 cache expectation generator and a check circuitry. The L2 cache expectation generator obtains information from a global memory precise control circuitry according to a multi-core consistency protocol and generates an expected result. The check circuitry is responsible for comparing the expected result with an actual result, thus implementing determination of multi-core interconnect's access accuracy to the L2 cache without delay.

Abstract: A processor achieving a zero-overhead loop, includes instruction stream control circuitry and loop control circuitry. The loop control circuitry includes loop address detecting circuitry and loop end determining circuitry. By combining instructions and hardware, the loop control circuitry eliminates additional control instructions required b each loop iteration and can achieve loop acceleration with zero overhead, thereby improving the loop execution efficiency.

Abstract: Disclosed is a processor having multiple operating modes, comprising: a first mode resource storage circuitry configured to store first mode resources when the processor is operating in a first mode, wherein the first mode resource storage circuitry comprises a resource mapping circuitry configured to provide second mode resources to the processor operating in the first mode; a second mode resource storage circuitry configured to store the second mode resources when the processor is operating in a second mode; and an access control interface communicatively coupled to the resource mapping circuitry and the second mode resource storage circuitry, the access control interface configured to provide the resource mapping circuitry with an access to the second mode resource storage circuitry.

Abstract: Embodiments of the present disclosure provides a device for implementing resource index replacement, comprising an instruction scheduling unit configured to receive a first type resource index from a resource allocating unit and then issue an instruction to an instruction executing unit for execution, to receive a second type resource index from the resource allocating unit, to execute the instruction from the instruction scheduling unit, and to issue a result of the instruction execution and the second type resource index to a result storing unit. The result storing unit comprises a plurality of resource for storing instruction execution results and execution results. The result storing unit is configured to allocate the first type resource index to an instruction entering the instruction scheduling unit and to allocate the second type resource index to an instruction entering the instruction execution unit.

Abstract: Embodiments of the disclosure provide an apparatus for adding a protection function for an indirect access memory controller. The apparatus can include: a bus monitoring unit configured to monitor a bus address, perform permission authentication if a register controlling operation is detected, and configure a list entry if a permission list configuring operation is detected; an permission list unit configured to partition a memory space into several virtual memory protection areas and independently set an access permission attribute (i.e.: readable, writable, erasable, etc.) of each memory area; a window register information bus configured to provide window register information, i.e.

Abstract: The present disclosure provides a method and an apparatus for erasing or writing Flash data. The method includes: reading an instruction for erasing or writing the data, the instruction for erasing or writing the data carrying start address information and end address information of a Flash memory where an operation of the instruction is to occur; querying whether the start address information and the end address information are in an address information table including one or more address ranges; and processing the instruction based on a result of the querying.

Abstract: The present disclosure provides a data computing system. The data computing system comprises: a memory, a processor and an accelerator, wherein the memory is communicatively coupled to the processor and configured to store data to be computed and a computed result, the data being written by the processor; the processor is communicatively coupled to the accelerator and configured to control the accelerator; and the accelerator is communicatively coupled to the memory and configured to access the memory according to pre-configured control information, implement a computing process to produce the computed result and write the computed result back to the memory. The present disclosure also provides an accelerator and a method performed by an accelerator of a data computing system. The present disclosure can improve the execution efficiency of the processor and reduce the computing overhead of the processor.

Abstract: The present disclosure provides a multi-core processor. The multi-core processor comprises a plurality of cores and a debug circuit, the debug circuit comprising debug circuits in the same number as that of the cores, transmission controllers in the same number as that of the cores, and a master control circuit, each of the debug circuits being connected to one core and one transmission controller, respectively, and all transmission controllers being connected to the master control circuit. Each of the debug circuits is configured to generate a debug event signal and respond to the generated debug event signal or received debug event signals generated by other debug circuits. Each of the transmission controllers is configured to respectively control transmission of the debug event signal between the respectively connected debug circuit and the master control circuit. The master control circuit is configured to forward debug event signals among different transmission controllers.

Abstract: Embodiments of the present disclosure provide a protective apparatus for an indirect access memory controller. The apparatus can include: a bus monitoring unit configured to monitor a bus address and detect an operation type of a bus accessing the indirect access memory controller, update a corresponding window register if the operation type is a window register operation, initiate permission authentication if the operation type is a register controlling operation, and perform list entry configuration if the operation type is a permission list configuration operation; a window register unit configured to store operation addresses of different access types; a permission list unit configured to partition a memory space into several virtual memory protection areas, and independently set a access permission attribute for each memory area; and an unauthorized operation processing unit configured to process a subsequent operation performed when a permission violating access occurs.

Abstract: The present disclosure provides a storage data encryption and decryption method, including: providing a true random number generator configured to generate a plurality of keys; providing a data memory configured to store data and a key memory configured to store keys, and writing the keys into the key memory; and providing a data reading and writing interface module configured to read and write data, and providing a data encryption and decryption module configured to read the keys and perform encryption and decryption operations. The data written by the data reading and writing interface module is encrypted by the data encryption and decryption module and written into the data memory. The data read from the data memory is decrypted by the data encryption and decryption module and read to the data reading and writing interface module.

Abstract: The present disclosure provides a serial communication device. The device includes: a first interface module communicatively coupled to an advanced bus of a master machine, a second interface module communicatively coupled to a data interface of a slave machine, a control module, a transceiving enable module, a shift register module and an interrupt generating module.