Abstract: Technology for translating a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the behavior, or other functionality, of multiple circuit portions, with at least some of the multiple circuit portions having multiple components. The technology includes determining components across the multiple circuit portions of the behavioral description that have commonalities, and synthesizing the structural description with a description of a shared circuit portion instead of individual structural descriptions of the components having the determined commonality. The synthesized structural description may be organized according to a different hierarchical structure than that of the behavioral description.
Type:
Grant
Filed:
August 16, 2013
Date of Patent:
November 11, 2014
Assignee:
C2 Design Automation
Inventors:
Michael Scott Meredith, Stephen B. Sutherland
Abstract: Technology for translating a behavioral description of a circuit into a structural description of the circuit is disclosed. The behavioral description may describe the circuit in terms of the behavior, or other functionality, of multiple circuit portions, with at least some of the multiple circuit portions having multiple components. The technology includes determining components across the multiple circuit portions of the behavioral description that have commonalities, and synthesizing the structural description with a description of a shared circuit portion instead of individual structural descriptions of the components having the determined commonality. The synthesized structural description may be organized according to a different hierarchical structure than that of the behavioral description.
Type:
Application
Filed:
August 16, 2013
Publication date:
February 20, 2014
Applicant:
C2 Design Automation dba Forte Design Systems
Inventors:
Michael Scott MEREDITH, Stephen B. Sutherland
Abstract: A data path optimization element is used in a behavioral synthesis process to optimize portions of an algorithmic description of a digital logic circuit. Directives are provided in the algorithmic description to identify subsets of the algorithmic description that can be extracted and optimized. The optimization includes identification of certain operators, function calls, conditional statements, or other relationships in the subset, and then compression of the extracted subset into or more data path components in a building block. The building block thus generated is substituted back into the algorithmic description and used in subsequent operations during the behavioral synthesis process, thereby leading to a more optimum design in terms of area, performance, power characteristics, or other characteristic(s).