Abstract: A hardware design language V++ is described. V++ provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V++ each program is directly interpreted as a network of communicating finite state machines. The composition of two V++ programs is a V++ program, with well-defined, deterministic semantics.
Type:
Grant
Filed:
April 22, 1999
Date of Patent:
July 16, 2002
Assignee:
Cadance Design Systems, Inc.
Inventors:
Patrick C. McGeer, Szu-Tsung Cheng, Michael J. Meyer, Patrick Scaglia