Patents Assigned to Cadenca Design Systems, Inc.
  • Patent number: 6348814
    Abstract: A buffer circuit and method provide substantially constant output signal edges to facilitate service as a bus driver with enhanced timing flexibility. The buffer circuit includes a NOR gate and a NAND gate for driving output pulldown and pullup transistors. The initiation of current flows through the NOR and NAND gates is controlled by an environmentally adaptive reference circuit. First and second transistors are provided respectively between the NAND gate and the pullup transistor, and between the NOR gate and the pulldown transistor, to produce enhanced sourcing and sinking currents. The enhanced sinking and sourcing currents are timely terminated by switching of the pulldown and pullup transistors to save energy.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: February 19, 2002
    Assignee: Cadenca Design Systems, Inc.
    Inventor: LuVerne Peterson