Abstract: Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified.

Abstract: A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.

Abstract: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring directions. Other embodiments provide a method of manufacturing an integrated circuit (“IC”) that has a plurality of wiring layers. The method specifies a layout of the IC by using a wiring model that specifies more than one preferred wiring direction for at least a region of a particular wiring layer. The method then uses the layout to fabricate the integrated circuit.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.

Abstract: A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

Abstract: A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n?1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

Abstract: An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the nets extend when linking cells forming different modules. The layout system automatically inserts buffers into selected segments of the nets to reduce signal path delays through the nets and assigns the inserted buffers to selected modules. However the layout system inserts buffers only into those net segments for which a buffer insertion would not alter the number of ports any module needs to accommodate the net.

Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.

Abstract: A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits.

Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided design tool processes the layout data to generate a separate database for each layer of the IC, including a separate table corresponding to each grid line of that layer. Each table includes a separate table entry corresponding to each conductor to reside along the table's corresponding grid line, each table entry indicating nominal dimensions and position of its corresponding conductor. The tool sorts grid line tables within each layer's database in an order in which their corresponding grid lines are arranged on that layer, and sorts entries in each table in an order in which their corresponding conductors are to appear along the table's corresponding grid line.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The method defines several nodes in the region. The method then specifies a plurality of edges in the region. Each edge is between a pair of nodes, and some edges are neither perpendicular nor parallel to some of the edges. The method uses the edges to define routes in the region.

Abstract: A method of determining a useful skew for a circuit design includes computing a slack value for each sequential cell in the circuit design, identifying modifiable sequential cells in the circuit design, and computing a target delay for each modifiable sequential cell. One or more sequential cells are discarded based on the slack values. A target slack value for each remaining sequential cell is determined. The remaining cells are sorted based on the target slack values to determine a minimum target slack value, and a delay for each cell is determined based on the minimum target slack value.

Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required clearance allows the global topological solution to be determined quickly. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution. Guide points are determined using the geometric routing solution. A detail router uses the guide points as corners when performing the actual routing.

Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.

Abstract: Some embodiments of the invention provide a method of determining whether a set of routes can be geometrically embedded in a region according to a particular wiring model. The method identifies a congestion graph that has a set of edges, where at least two edges are neither orthogonal nor parallel. For each edge, the method identifies the set of routes that intersect the edge. It then determines whether any edge is overcongested.

Abstract: Some embodiments of the invention provide a method of expanding a path in a space with dimensional states. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The method identifies a first expansion for the path from a start state to a first destination state. It then specifies a first cost function that expresses the cost of the first expansion. The first cost function is defined over the destination state. The method also identifies a second expansion for the path from a first portion of the first destination state to a second destination state. From a portion of the first cost function that is defined over the first portion of the first destination state, the method computes a second cost function that specifies the cost of the second expansion.