Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

Abstract: Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include receiving an electronic design at a verification environment. Embodiments may also include performing a simulation of a portion of the electronic design in an X-propagation mode. Embodiments may further include determining whether the simulation is entering an element during a time range and determining whether a clock/reset associated with the element has an active X-edge. If the clock/reset has an active X-edge, embodiments may include preventing a recordation of coverage metrics during the time range.

Abstract: The embodiments described herein provide for methods and systems for removing power supply induced jitter from a Phase Lock Loop to provide a Power Supply Induced jitter-free clock signal to a system-on-a-chip and GDDR6 DRAM interface. In operation, a circuit reduces a DC offset between a reference voltage and a voltage regulator output to identify low frequency noise on the voltage regulator output to apply as negative feedback to reduce the low frequency noise on the voltage regulator output. The bandwidth of the circuit is increased to detect high frequency noise, which is applied as negative feedback on the voltage regulator output. Very high frequency noise is then detected and applied as negative feedback to the voltage regulator output. The circuit outputs a regulated output equal to the reference voltage and immune to the low, high, and very high frequency noise of power delivery network supply to the regulator.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model.

Abstract: The present disclosure relates to electronic circuit design, and more specifically, to determining the computational requirements of fully synthesizing a printed circuit board and/or package. Embodiments may include receiving, using a processor, one or more PCB electronic design files and determining whether the PCB electronic design files include data required for a synthesis engine. If any data is missing, the method may include inferring one or more parameters using an inference engine and providing the one or more parameters to the synthesis engine, wherein the synthesis engine includes at least one of a placement, via assignment, routing, and metal pouring processes. The method may also include collecting process data from the placement, via assignment, routing, and metal pouring processes and training a machine learning system using the process data.

Abstract: The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include a differential amplifier including a first transistor and a second transistor, wherein the differential amplifier includes a peak-generating path and a peak-reduction path. Embodiments also include at least one switch and at least one capacitor located between a source and a drain of at least one of the first transistor and the second transistor to create a capacitive path between the source and drain, wherein the at least one switch and at least one capacitor are configured to reduce bandwidth.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include receiving, using at least one processor, a user input corresponding to a command in an electronic design automation environment. Embodiments may further include comparing the user input with a portion of an electronic design database. Embodiments may also include providing a final command suggestion based upon, at least in part, the comparison.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, at a graphical user interface, an indication of a desired wire creation associated with an electronic design and determining a plurality of routing solutions, based upon, at least in part, the desired wire creation. Embodiments may further include simultaneously displaying the plurality of routing solutions at the graphical user interface, wherein a predicted preferred routing solution is graphically emphasized. Embodiments may also include receiving a selection from a user, at the graphical user interface, of one of the plurality of routing solutions and storing the selection for subsequent use.

Abstract: Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.

Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using a processor, an initial data set associated with an electronic design and performing a built in self-discovery (BISD) analysis based upon, at least in part, the initial data set. Embodiments may include displaying, at a graphical user interface, a plurality of tiered, user-selectable options and receiving a user input corresponding to a selection of at least one of the plurality of tiered, user selectable options. Embodiments may also include tuning the plurality of tiered user selectable options based upon, at least in part, the user input.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

Abstract: The present disclosure relates to a computer-implemented method for routing in an electronic design. Embodiments may include receiving, using at least one processor, global route data associated with an electronic design as an input and generating detail route data, based upon, at least in part, the global route data. Embodiments may further include transforming one or more of the detail route data and the global route data into at least one input feature and at least one output result of a deep neural network. Embodiments may also include training the deep neural network with the global route data and the detail route data and predicting an output associated with a detail route based upon, at least in part, a trained deep neural network model. Embodiments may also include generating routing information for each routing grid.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving an electronic design having a plurality of objects associated therewith. Embodiments may further include allowing, at a graphical user interface, a user to define at least one user-refined filter selected from the group consisting of an instance pin filter, a library cell instance filter, a clock pin filter, and a net filter. Embodiments may also include generating one or more constraints based upon, at least in part, the user-refined filter.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include performing, using a processor, an electronic design process on a portion of an electronic design. Embodiments may also include automatically monitoring the electronic design process on a periodic basis using a pulse monitor to acquire one or more sampling results and storing the one or more sampling results. Embodiments may further include providing, during the electronic design process, the one or more sampling results to a graphical user interface.