Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: A design verifier includes a bounded model checker, an abstractor and an unbounded model checker. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If no counterexample is found, the abstractor generates an abstracted design description using a proof generated by the bounded model checker. The unbounded model checker verifies the property of the abstracted design description. If a counterexample is found, the bounded model checker increases K and verifies the property to the new larger depth. If no counterexample is found, the design is verified.

Abstract: A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the parameter. In some embodiments, the generated sub-network has several circuit elements, performs two or more functions, or is stored in an encoded manner. A method for producing a circuit description of a design that (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure, and (4) replaces the candidate sub-network with the replacement sub-network in certain conditions. In some embodiments, this method is performed to map a design to a particular technology library. Some embodiments provide a data storage structure that stores sub-networks based on parameters derived from the output functions of the sub-networks.

Abstract: A non-uniform transmission line, including at least a first section with length L1, uniform width W1 and thickness h1, and a second section with length L2, uniform width W2 and thickness h2, joined together to form a composite structure and arranged in any of at least three distinct configurations. The composite structure (first section plus second section) may be periodic or non-periodic. Length and/or width and/or thickness of each of the two sections may be varied to provide desired values for characteristic impedance, cutoff frequency and/or time delay for signal propagation.

Abstract: Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. The method identifies groups of related sub-region configurations. For each group, the method stores a base set of routes. For each configuration in each group, the method also stores an indicia that specifies how to obtain a related set of routes for the particular configuration from the base set of routes stored for the configuration's group.

Abstract: Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments concurrently select an optimal pair of wiring and illumination configurations. Other embodiments select an illumination configuration based on the selected wiring configuration. Yet other embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. In some embodiments, this selection entails selecting a stepper lens for each particular layer of the IC layout.

Abstract: A system for dynamically compressing circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first and second branches for simulation, 2) if two or more leaf circuits of the circuit having a substantially same isomorphic behavior, representing the two or more leaf circuits as a merged leaf circuit, 3) creating a first port connectivity interface dynamically for the group of leaf circuits in response to the merged leaf circuit, where the first port connectivity interface communicates changes in signal conditions among the group of leaf circuits, and 4) simulating the group of leaf circuits in accordance with the first port connectivity interface.

Abstract: A federated system and methods and mechanisms of implementing and using such a system is disclosed. In some embodiments, one or more mappings are created between a taxonomy view at a node and one or more taxonomies of one or more data sources. The one or more data sources can then be accessed via the taxonomy view. In other embodiments, one or more mappings are created between content from different data sources and content from those data sources are merged using the one or more mappings.

Abstract: An automated method and system for managing simulation results of a virtual circuit. Data related to the virtual circuit is accessed. The virtual circuit is subject to a simulation. An initiation of each of one or more transactions occurred during the simulation is identified, and data related to the one or more transactions during the simulation is collected. Upon receipt of a user request, the collected data related to the one or more transactions is output, displayed, stored or made available for review or further processing.

Abstract: A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Abstract: A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.

Abstract: A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more intelligent metrology and reduces cycle time.

Abstract: A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: The disclosure presents a formulation to support simulatable subset (also known as ‘simple-subset’) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the ‘simple-subset’ is transformed to a set of basic formulas. Verification engines are required to support the basic formula only. The basic formula is a form of automata in the property specification language. This is called SERE implication. The efficiency of verification is dependent on size of automata. Miscellaneous opportunistic rules are applied to optimize SERE implication formulas.

Abstract: A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.

Abstract: The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and where the at least one local region is adapted to support non-integer multiple height rows. At least one cell is associated with the at least one local region formed, and the cell can be placed in the local placement grid of the local region.

Abstract: A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.