Patents Assigned to Cadence Design Systems
  • Patent number: 10540467
    Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and identifying at least one combinational loop associated with the electronic circuit design. Embodiments may also include extracting, for each component of the loop, a set of logic conditions and modeling the at least one combinational loop. Embodiments may further include providing a graphical user interface configured to display one or more constraint candidates and determining whether or not a conflict exists between constraint candidates. Embodiments may also include ranking the constraint candidates, based upon, at least in part, a number of loops disabled and one or more disabled loop characteristics.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 21, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Craig Franklin Deaton, Abner Luis Panho Marciano, Matheus Nogueira Fonseca, Ronalu Augusta Nunes Barcelos, Fabiano Cruz Peixoto
  • Patent number: 10540466
    Abstract: An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the received signals as waveform data records. During the runtime of emulating the DUT, the emulation computer may receive an upload request for the waveform data records from a workstation computer. In response to the request, the emulation computer may transmit the waveform data records to the workstation computer. The emulation computer does not have to pause or stop the runtime of emulating the DUT while transmitting the data records to the workstation computer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 21, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alon Kfir, Jennifer Lee
  • Patent number: 10540470
    Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: January 21, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Paul W. Kollaritsch
  • Patent number: 10541043
    Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 21, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Carl Alexander Wisnesky, II, Patrick Wayne Gallagher, Steven Lee Gregor, Norman Robert Card
  • Patent number: 10540461
    Abstract: A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: January 21, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shai Mizrachi, Eyal Gvili
  • Patent number: 10540464
    Abstract: The present embodiments relate to critical path aware voltage drop analysis. A method can include identifying a number of cell instances with largest individual power consumption values. The method can include identifying, by performing static timing analysis, a first number of circuit timing paths of an integrated circuit design with largest timing violations. The method can include identifying, by performing the static timing analysis, a second number of circuit timing paths of the integrated circuit design. Each of the second number of circuit timing paths has a timing violation and is formed by one or more of the identified number of cell instances. The method can include generating logic state toggle vectors by propagating logic states through the first and second numbers of circuit timing paths. The method can include performing voltage drop analysis on the integrated circuit design using the generated logic state toggle vectors.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: January 21, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Suketu Desai, Anshu Mani, Apurva Soni, Shivani Sharma, Avnish Varma, Xin Gu
  • Patent number: 10536147
    Abstract: The present disclosure relates to an apparatus including level shifter circuitry configured to convert a voltage between one or more multi-voltage domains. The apparatus may include an integrated circuit having a cross-coupled latch including a first weak transistor cross-coupled with a second weak transistor. The integrated circuit may further include a first strong transistor in parallel with the first weak transistor and a second strong transistor in parallel with the second weak transistor. The integrated circuit may further include an inverter configured to toggle at least one of the first weak transistor and the second weak transistor.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinod Kumar, Karishma
  • Patent number: 10534887
    Abstract: A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 14, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Sravasti Nair, Subhashis Mandal, Chandra Prakash Manglani, Nikhil Garg, Preeti Kapoor, Kanaka Raju Gorle
  • Patent number: 10536553
    Abstract: An emulation system comprises an outband traffic generating device comprising at least one field programmable gate array coupled to a host system. The outband traffic generating device is configured to transfer one or more bits via an outband channel to a register of an inband traffic generating device. The inband traffic generating device comprises at least one field programmable gate array coupled to a target system. The inband traffic generating device is configured to transfer the one or more bits via an inband channel to the outband traffic generating device.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Sharon Mutchnik, Hitesh Gannu, Ramesh Mogili
  • Patent number: 10534994
    Abstract: The present disclosure relates to a computer-implemented method for analyzing one or more hyper-parameters for a multi-layer computational structure. The method may include accessing, using at least one processor, input data for recognition. The input data may include at least one of an image, a pattern, a speech input, a natural language input, a video input, and a complex data set. The method may further include processing the input data using one or more layers of the multi-layer computational structure and performing matrix factorization of the one or more layers. The method may also include analyzing one or more hyper-parameters for the one or more layers based upon, at least in part, the matrix factorization of the one or more layers.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Piyush Kaul, Samer Lutfi Hijazi, Raul Alejandro Casas, Rishi Kumar, Xuehong Mao, Christopher Rowen
  • Patent number: 10534565
    Abstract: A device including an address extraction for a data burst associated with a host processor and to map the data burst to a memory according to a rotation is provided. The device includes a splitter to separate a first command that associates the data burst with a first round in the rotation, and a selection logic to select, from the first round in the rotation, a first bank group at the address in the memory to execute the first command, and execution logic to receive the data burst and the address in the memory to activate the first bank group at the address in the memory, and to schedule an execution of the first command based on an availability of a second bank group from the first round in the rotation. A system and a non-transitory computer readable medium storing instructions to use the device are also provided.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 14, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Bikram Banerjee, Anne Hughes, John M. MacLaren
  • Patent number: 10534625
    Abstract: Disclosed herein is an apparatus and method for emulating hardware. The apparatus includes a data array configured to store input data for an emulation cycle and a carry chain coupled to the data array receives one or more inputs from the data array. The carry chain is configured to generate output data in response to performing an arithmetic operation by a set of configurable logic gates using the one or more inputs in a pre-determined number of clock cycles. One or more processors are coupled to the carry chain and the data array, and are configured to emulate a logic gate function using at least the input data from the data array or the output data from the carry chain.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Beshara Elmufdi
  • Patent number: 10528691
    Abstract: A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one or a plurality of conditions.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: January 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventor: Meir Ovadia
  • Patent number: 10528644
    Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Wangyang Zhang, Hongzhou Liu
  • Patent number: 10528688
    Abstract: Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rameet Pal, Taranjit Singh Kukal, Rajesh Prasad Singh
  • Patent number: 10528689
    Abstract: A system and methods to verify a correctness of data formatted according to an IEEE P1687 (IJTAG) standard, in connection with migration of test patterns from an instrument level to a top level of an integrated circuit design. Data describing an integrated circuit at the instrument level and at the top level is read from Instrument Connectivity Language (ICL) files, Procedural Description Language (PDL) files, and hardware description language (HDL) files. The methods include at least one of verifying structural descriptions of the integrated circuit in the ICL files and verifying an ability to use chip level inputs to access instruments in the integrated circuit. The verification procedure is performed prior to a simulation in which a migrated test pattern is applied to the integrated circuit.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 7, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Rajesh Khurana, Vivek Chickermane, Dhruv Dua, Krishna Vijaya Chakravadhanula
  • Patent number: 10521097
    Abstract: Described herein is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where a routing system is implemented to generate a complete routing tree. A user interface is provided that captures users' design intent about topology of an electrical design, and the routing system adheres to that user's design intent about the topology throughout a layout process for the electrical design.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 31, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hoi-Kuen Lam, Chung-Do Yang, John Mario Wilkosz
  • Patent number: 10521531
    Abstract: The present disclosure relates to a method for formal verification of an electronic design. Embodiments may include receiving, using a processor, an electronic design having a plurality of clock configurations associated therewith and identifying a target clock configuration associated with the electronic design. Embodiments may also include receiving a range of clock factor values from a user, wherein each clock factor value corresponds to a frequency of the target clock configuration. Embodiments may further include selecting, via a formal engine, at least one clock factor value from the range and selecting, via the formal engine, at least one clock phase associated with the target clock configuration. Embodiments may also include performing formal verification of the electronic design, based upon, at least in part, the at least one clock factor value or the at least one clock phase.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 31, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frederico Nascimento-Yoshida, Matheus Nogueira Fonseca
  • Patent number: 10521543
    Abstract: Disclosed herein are embodiments of systems, methods, and products for dynamically determining and rendering a target resistance of a partially routed net between two circuit devices in an integrated circuit (IC) design and automatically resizing a wire segment being edited in real time based on the target resistance such that the fully routed net satisfies the maximum resistance constraint. Therefore, the embodiments disclosed herein simplify the circuit designer's job and improves design productivity. Unlike conventional systems, an EDA tool disclosed herein does not have to route the full net between two circuit devices to run design rule checking (DRC). Thus, the EDA tool does not require multiple iterations of fully routing a net and checking for DRC violations such that the maximum resistance constraint is not violated.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: December 31, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventor: Laurent Saint-Marcel
  • Patent number: 10515169
    Abstract: The present disclosure is directed towards electronic circuit design and verification. Embodiments may include receiving, using a processor, source code corresponding to at least a portion of an electronic design and generating at least one coverage model for each of a dynamic verification and a formal verification. The method may further include determining a formal data set including stimuli coverage status, cone of influence coverage status, and proof coverage status and consolidating the formal data set using a user-programmable consolidation function to generate a combined formal coverage data set.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: David Ryan Spatafore, Amit Verma, Anubhav Srivastava