Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.

Abstract: An automated system and method for determining flip chip connections involves generating a first projection that includes representations of bumps arranged over a core of the flip chip and generating a second projection that includes representations of I/O pads arranged around the core. The first projection is generated by drawing a line through each bump between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the bump. The outer portion of the flip chip is traversed, and the first projection is generated based on the order in which bump representations are encountered. The second projection is generated by drawing a line through each I/O pad between a location of the flip chip and an outer portion of the flip chip and marking a location where the line terminates at the outer portion with a representation of the I/O pad.

Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.

Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Abstract: In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.

Abstract: A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.

Abstract: A method and apparatus for generating user clocks in a prototyping system is disclosed. A prototyping system has a plurality of programmable logic chips that are each programmed with one or more partition of a prototyped circuit design. For a circuit design having multiple user clock signals, each partition uses some or all of the user clocks. A reference clock signal is externally generated, and received by each of the programmable logic chips. Using a phase-locked loop, a plurality of in-phase higher frequency clock signals are generated from the reference clock signal. The user clock signals are then generated from these higher frequency signals using a plurality of divider circuits. Reset circuitry implemented in one of the programmable logic chips transmits a common reset signal to the divider circuits, maintaining the phase relationship of each user clock across the programmable logic chips.

Abstract: A system, method, and computer program product is disclosed for performing electrical analysis of a circuit design. A voltage-based approach is described for performing two-stage transient EM-IR drop analysis of an electronic design. A two-stage approach is performed in some embodiments, in which the first stage operates by calculating the voltage at certain interface nodes. In the second stage, simulation is performed to simulate the circuit to concurrently obtain the current at the interface nodes.

Abstract: Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

Abstract: In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.

Abstract: Certain circuit models include design parameters that reflect user choices and statistical parameters that reflect modeling uncertainty. For each performance goal (e.g., a one-sided performance goal), a closest point of failure in the statistical parameters is used to identify a statistical corner that characterizes a specified tolerance for that performance goal. Adjusting the design parameters to improve performance for these corners improves overall performance and corresponding yields.

Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.

Abstract: A method of extracting capacitance from a layout record includes imposing voltages on conductors in a layout record, and determining a total charge for each of the conductors to obtain a capacitor element for the conductors. A method of extracting capacitance from a layout record includes matching a configuration of conductors in a layout record against a reference pattern, and determining an extracted capacitance for the conductors based at least in part on the reference pattern. A method of extracting capacitance from a layout record includes providing a layout record of a circuit design, the layout record having data representing conductors and metal fill, and extracting capacitance to determine a set of capacitors between the conductors, the set of capacitors accounting for the metal fill.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.