Abstract: This disclosure relates to signal observability rating. In an example, a method can include propagating a clock signal through a respective module of a circuit design in a forward and backward direction, evaluating clock signal propagation results for the respective module based on a forward and backward clock signal propagation of the clock signal to compute an observability rating for a data signal to be processed by the respective module during formal verification, and updating a current observability rating of the respective property for the data signal to the computed observability rating.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling coefficient associated with a controlled source of the circuit model. Embodiments may further include extracting a transmission line mode from the circuit model and linking the circuit model, at least one via, and the transmission line mode to an external circuit to generate a modeled system. Embodiments may also include solving the modeled system using a modified nodal analysis.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

Abstract: According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

Abstract: Systems and methods for IC chip design testing can include a hardware emulator, having circuitry to emulate functionalities of an integrated circuit chip design and a buffer, detecting an assertion failure event indicative of a failed assertion on one of the functionalities, and storing a message indicative of the assertion failure event in the buffer. The circuitry can transfer, asynchronously relative to execution of the hardware emulator, the message from the buffer to a software host device without halting the execution of the hardware emulator. The software host device can receive the message indicative of the assertion failure event, and execute, asynchronously relative to the execution of the hardware emulator, at least one fail action instruction associated with the assertion failure event.

Abstract: Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.

Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

Abstract: Various embodiments provide for routing a circuit design based on adjusting a routing demand. More specifically, some embodiments implement routing demand smoothing of a grid cell, routing overflow spreading of a grid cell, or some combination of both prior to detailed routing of a circuit design, which can result in improved detailed routing over conventional routing techniques.

Abstract: An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

Abstract: An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Abstract: Various embodiments provide a method or system that implements a two-tap decision feedback equalizer by applying a first tap and a second tap on a first symbol of a data signal, each of the first and second taps having a first and second polarity to generate a first corrected data symbol and a second corrected data symbol. The first corrected data symbol and the second corrected data symbol is provided to a comparator to select a data symbol. The output of the comparator is provided to a clock data recovery circuit along with a previous data symbol of the data signal preceding the first data symbol.

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

Abstract: A pseudorandom logic circuit may be embedded as a hardware within an emulation system, which may generate pseudorandom keephot instructions. A masking logic may mask out portions in each pseudorandom keephot instruction, which may change state elements during execution. A cluster of emulation processors may execute masked pseudorandom keephot instructions to consume power when not executing mission instructions. The cluster of emulation processors may run keephot cycles, during which the cluster of emulation processors may execute the pseudorandom keephot instructions causing the cluster of emulation processors to continue consuming a roughly constant amount of power, either at a same or different voltage level, but supposed outputs of the pseudorandom keephot instructions may have no impact upon inputs and outputs generated during mission cycles.

Abstract: A fault rules engine generates a plurality of fault rules files, each of the fault rules files is associated with a respective cell type of a plurality of cell types in an integrated circuit (IC) design. Each fault rules file includes data quantifying a nominal delay for a given two-cycle test pattern and data quantifying a delta delay for the given two-cycle test pattern corresponding to a given candidate defect of a plurality of candidate defects of a given cell type of the plurality of cell types in the IC design. An IC test engine extracts an input to output propagation delay for each cell instance from a standard delay format (SDF) file for the IC design and generates cell-aware test patterns for each cell instance of each cell type in the IC design based on the plurality of fault rules files and the extracted input to output propagation delays.