Patents Assigned to Cadence Design Sysyems, Inc.
  • Method and mechanism for performing DRC processing with reduced passes through an IC design
    Patent number: 7418682
    Abstract: A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associated with a family of related polygons.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: August 26, 2008
    Assignee: Cadence Design Sysyems, Inc.
    Inventor: Eitan Cadouri