Abstract: Methods and systems provide aspects of electronics layout design including copying of layout element(s) and graphically defining a one-to-one correspondence between two elements. An exemplary method may include defining a cloning constraint for a layout, rendering a user interface (UI) to display at least one of a schematic and form representation of the layout, and receiving a selection of at least one element in the layout. The method may create a movable drag set based on the selection, and responsive to a matching of at least one element of the drag set with another element in the layout, performing a one-to-one correspondence for the matched elements. The matching may be an overlap of at least one element in the drag set with an element in the layout having the same master.

Abstract: A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.