Abstract: Methods and systems provide creating and reporting of path annotations and renaming a state node using the path annotations for high level synthesis (HLS). In an embodiment, a method to annotate a state node includes identifying labels and pragmas specified in a high-level language input model for wait statements and function calls, and can also accommodate loops. In an embodiment, a method to display and/or report annotation information for a given state node includes displaying a state node name, an associated path annotation, and/or an associated hierarchical path. In an embodiment, a method to rename a state node based on a user-specified name includes using annotation information to locate a target state node and associating the target state node with the user-specified name or an automatically-created name based on the user-specified name. In an embodiment, a name specified for a state node can persist through successive runs of an HLS tool.

Abstract: A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable number of input addends and outputs a number of results. Embodiments perform one to four multiplications together, depending on the number of bits (eight, 16, 24, or 32) selected for the input operands. Embodiments output 20-bit, 40-bit, or 80-bit multiply-accumulate results at rates of at least 1.1 GHz. Embodiments support signed inputs, negated multiplication products, and Q-format data. A hybrid sign extension management approach improves performance for 80-bit outputs.

Abstract: A fused-multiply-add system is disclosed. The fused-multiply-add system includes a multiplier to multiply first and second operands and to provide at least one product. The fused-multiply-add system also includes an alignment shifter for aligning a third operand with the at least one product to provide an aligned third operand. The fused-multiply-add system also includes an adder and a subtractor coupled to the multiplier and the alignment shifter for performing two asymmetrical additions in parallel paths. The fused-multiply-add system also includes at least one leading zero counter for counting a number of leading zero bits provided by at least one of the adder and the subtractor to provide at least one normalization shift amount. Finally, the fused-multiply-add system includes a multiplexer coupled to the adder and the subtractor for providing an appropriate output based upon a sign bit.

Abstract: Some embodiments correlate various manufacturing or design information or data with patterns used to represent electronic designs and provide pertinent pattern-based information to metrology, fabrication, or testing tools to enhance their performances of their intended functions. Some embodiments further utilize cross-design or cross-process analytics to perform various pattern-based analyses on electronic designs. Some embodiments perform squish analysis with a squish pattern library on an electronic design to represent the electronic design with squish patterns by performing pattern matching, pattern decomposition, and pattern classification process.

Abstract: A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input device, a generation model and a coverage model from a user. The method may also include using a processor, identifying a coverage item in the coverage model and finding a corresponding element in the generation model corresponding to the coverage item. The method may further include using a processor translating a coverage requirement associated with the coverage item into a distribution directive; and using a processor, solving the generation model with the distribution directive on the corresponding element, to obtain a set of stimuli.

Abstract: Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

Abstract: An apparatus and method for identifying an optimal harmonic number of a circuit are disclosed. In a simulation of the circuit, a periodic input waveform up to a particular number of periods is applied to the modeled circuit and an output waveform is obtained in response. In response to detection of a steady state response of the output waveform, embodiments simulate the circuit by applying an additional period of the periodic input waveform and obtaining the output waveform corresponding to the additional period of the periodic input waveform. A time domain power value and a frequency domain power value are calculated using the output waveform corresponding to the additional period of the periodic input waveform. Embodiments detect a harmonic of the output waveform corresponding to the additional period of the periodic input waveform at which the time domain power value and the frequency domain power value converge with each other.

Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.

Abstract: A CoDec in a design for test integrated circuit. In embodiments described herein, portions of the CoDec are distributed over the area of the IC. In particular, both the compressor and the decompressor may be distributed over the IC. To this end, XOR gates are located locally to the scan chains over the area of the chip to reduce wire length back to the input/output test pins. The compressor and decompressor may be distributed in a 2-dimensional grid. The compressor may XOR each scan chain in two different directions such that a fault may be resolved back to a specific region of the IC.

Abstract: A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools.

Abstract: An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.

Abstract: A system and method are provided for selectively coupled parasitic compensation for voltage offset in an electronic circuit. At least one compensation cell is coupled to an input stage for the circuit. The compensation cell includes an isolation node disposed in spaced manner from control and sampling nodes defined by the input stage. The isolation node is configured to form first and second parasitic capacitances respectively with the control and sampling nodes during system operation. An offset switch is coupled to the isolation node and selectively set between first and second switching states. The offset switch selectively either maintains or interrupts a series coupling of the first and second parasitic capacitances between the control and sampling nodes; and, the sampling node is thereby adaptively adjusted in voltage by a predetermined portion of a control signal applied to the control node.

Abstract: Methods and systems provide a partitioned IP core and hierarchical power management to reduce power consumption and footprint size of an “always-on” pulse density modulation (PDM) sensor system. The IP core may be partitioned into a register transfer level (RTL) block and a firmware block. The RTL may include a first stage decimation filter, storage, and, optionally, a sound energy detector. The firmware block may include subsequent decimation filter(s) and sensor processing logic, e.g., a sound trigger algorithm. In operation, the firmware block may conserve energy by being in a power-off or power-saving mode by default. Responsive to a trigger by the sound energy detector, the firmware block may wake up, receive data from the RTL block, and process the data. The sound energy detector may output the trigger based on characteristics of the received sample such as signal strength, noise strength, and type.

Abstract: The present disclosure relates to a computer-implemented method for electronic design verification. Embodiments may include providing, using one or more processors, an electronic design verification environment having a plurality of randomize calls associated therewith. Embodiments can also include selecting one of the plurality of randomize calls for analysis at a constraint solver engine and iteratively analyzing the selected randomize call using a plurality of constraint solver algorithms. Embodiments can also include automatically determining a most effective constraint solver algorithm for the selected randomize call.

Abstract: This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.

Abstract: An executable circuit design is used to generate waveforms, from which behaviors of the circuit are captured. The behaviors and various combinations thereof can then be saved in a database, along with descriptions and other metadata about them, thereby generating a behavioral index of the circuit design code. Behavioral indexing of circuit designs allows a user to maintain an indexed behavior database, track changes in behaviors as the circuit design's executable description evolves, and figure out how the executable description can be reused in different projects. When applied to digital design development, it facilities the current design and verification effort, as well as design reuse down the line.

Abstract: A chip select signal is trained where the chip select signal is delayed to centrally align its pulses with a positive edge of a memory device's clock cycle. Over repeated iterations, the memory device stops its clock for an interval and a delayed pulse of the chip select signal is generated. The pulse delay is incrementally changed with each iteration. When the delay results in the trailing edge of the delayed pulse aligning with the positive edge of the last cycle before the stoppage interval, the memory device captures the contents of a computer bus, thus detecting a trailing edge delay value. When the delay results in the leading edge of the delayed pulse aligning with the positive edge of the last cycle, the device no longer captures the contents, thus detecting a leading edge delay value. A value between these values is then set as the optimal delay.

Abstract: Methods, systems, and integrated circuits for decompressing a set of scan input data in a Design for Test (DFT) application, in which implementation may include determining a number of scan inputs to applied circuit from automated test equipment (ATE). Based on the number of scan inputs, another aspect of implementation may involve generating a 2-dimensional grid on the integrated circuit (IC). Another implementation aspect may involve decompressing the scan inputs from the ATE according to decompression logic that is sequentially distributed such that the grid can locally apply the last stage of the decompression logic. In accordance with aspects of the method, the physical structure of an IC decompression logic is more accessible to individual scan chains and reduces congestion on board the IC.

Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

Abstract: Methods and computer-readable media for effecting physically efficient scans of integrated circuit designs may include selecting a two-dimensional grid size for exposure to the method, the two-dimensional grid having a size that includes a first side length, a second side length, and a number of flops. The method is performed to select a two-dimensional grid size that maximizes compression efficiency and limit wiring congestion on the IC. In one aspect, the method may be performed on each region of the grid that maintains one of a respective first side length and a respective second side length greater than one, including selecting a larger side, determining if the larger side is odd or even, and dividing the grid along the larger side into two regions each having a proportion of the flops. The scans of the resulting regions are efficient, and consequently facilitate integrated circuit design and subsequent manufacture.