Abstract: An electronic device package with enhanced heat dissipation effect comprises a lead frame and an outer frame with electrically insulating surface. The outer frame encloses the electronic device with a predetermined gap therebetween. The lead frame has a plurality of inner leads extending to the upper surface of the electronic device and a plurality of outer leads enclosing the outer surface of the outer frame. Each inner lead and each outer lead are linked by a slanting portion. The plurality of outer leads includes at least one ground outer lead with larger cross section area than other outer leads. Therefore, the heat generated by the electronic device can be conducted outside through the ground outer lead when the ground outer lead is connected to other device.

Abstract: The present invention proposes a heat spreader for a ball grid array package. In a ball grid array package, a chip is attached to a first surface of a substrate by adhesives. Bonding areas on the first surface of the substrate adjoining to where the chip is attached are connected to the chip through metal leads. Solder balls formed on the first surface of the substrate are soldered to another device such as a motherboard. A metal heat spreader having a protuberance covers on the chip. The protuberance of the heat spreader contacts the chip to enhance the heat dissipating effect of the chip.

Abstract: A chip scale package for packaging an IC chip includes a package frame displaced from the side and bottom surfaces of the IC chip by a predetermined gap and a pair of leads symmetrically extending in opposite directions. Each lead has an inner lead portion coupled to a bonding point on the top surface of the IC chip, and an outer lead portion bent and contoured in such a way that to follow the shape of the outside surface of the package frame. The lead further includes a connecting segment extending between the inner lead portion and the outer lead portion. Under heat induced stress, an angle between the connecting segment and the wall of the package frame changes causing displacement of the IC chip from its original position, and the gap between the surfaces of the IC chip and the package frame absorbs deviations in position of the IC chip, to cushion the stress effect.

Abstract: An indicator based on the present invention for indicating the adhesion status between a substrate and the encapsulation layer of a packaged electronic device is characterized in that at least one indicating pattern and one indicating region surrounding the indicating pattern are formed on the substrate, the adhesion between the indicating pattern and the encapsulant is very good while that between the indicating region and the encapsulant is relatively poor, both the indicating pattern and the indicating region are covered by molding encapsulant which is stripped off when having become hardening, thereby the status of the indicating pattern appearing after stripping off the encapsulant can indicate the adhesion quality (integration quality) between the encapsulation layer and the substrate. The indicator realizes a non-destructive quality checking process in which each electronic device can be checked to achieve one hundred percent of quality control.

Abstract: The present invention discloses a heat sink for enhancing heat dissipation efficiency of an electronic device. The heat sink includes a base for accommodating at least an electronic device, a dissipation plate overlaid on the base for absorbing and dissipating heat generated by the electronic device, and a fan for generating airflow. A side wall of the base is formed with at least an air duct for guiding the airflow generated by the fan through a bottom of the electronic device, thereby enhancing heat dissipation efficiency of the electronic device.

Abstract: An electronic device cooling arrangement includes a heat sink bonded to a substrate above a chip on the substrate, the heat sink having a mounting section bonded to the substrate, a face panel section suspended above the chip and defining a tapered center through hole, and a supporting frame section connected between the face panel section and the mounting section, and a tapered heat conductive block mounted in the tapered center through hole and bonded to the chip for quick dissipation of heat from the chip.

Abstract: A substrate method of repairing a array including the step of cutting longitudinal frame sections, transverse frame sections and connecting portions of a prime substrate array to remove a defective substrate from it, permitting the prime substrate array to be separated into two separated substrate arrays; and the step of fastening the cut longitudinal frame sections, transverse frame sections of the two separated substrate arrays together, so as to form a repaired substrate array.

Abstract: A method for connecting TEHS to PBGA and a modified connecting structure for TEHS and PBGA are disclosed. The structure improves both heat dissipation efficiency of PBGA by TEHS with high heat conductivity and electrical performance of PBGA by TEHS which is electrically connected to the circuit in PBGA substrate. There are two methods of connecting TEHS to PBGA, including metallic soldering and nonmetallic adhesion. In the metallic soldering, the contact region of the TEHS is covered with a layer of solder tin and soldered to metallic contact region of the growing circuit in the substrate. In the nonmetallic adhesion, the metallic contact region of the growing circuit is covered with a layer of conductive resin. The TEHS is adhered and fixed to the metallic region by curing the conductive resin.