Abstract: The invention provides a method and apparatus for enhancing apparent image resolution by way of multi-line interpolation.

Abstract: Authentication mechanism for interactive home entertainment systems using plug-in cards which do contain software as well as cards which do not contain software. A security bit stream is generated by circuitry on the card and checked by the base system while the system is operating, but only a single signal line of the interface is used for the bit stream. The card also includes a ROM which contains data to be downloaded to the base system. The ROM data is downloaded to the base system via the same signal line of the interface as the serial bit stream. The signal line is used for ROM data download while the base system asserts a "reset" signal, and is used to carry the serial bit stream for authentication purposes whenever the reset signal is negated.

Abstract: A plurality of "snoop advisory" bits are maintained by snoop management circuitry externally to the processor structure. Each snoop advisory bit corresponds to a respective "snoop advisory page" of the memory address space. Three parallel processes take place with respect to these bits. First, in response to each read access by the processor structure, if the read access is of a predetermined type (such as a cache line fill operation with intent to modify), snoop management circuitry writes a "snoop yes" value into the snoop advisory cell corresponding to the snoop advisory page which includes the address of the processor's access. Second, in response to each access by another device which shares the address space with the processor structure, a snoop request is issued to the processor structure, but only if the snoop advisory cell corresponding to the snoop advisory page which includes the address of the device's access, contains the "snoop yes" value.

Abstract: A graphics system includes triangle-engine for real-time rendering into a displayable frame-buffer of image data derived from vertex-based deferred instructions. The system uses homogeneity values (1/w values) for z-buffer-like occlusion mapping as well as for texture mapping. Depth resolution is enhanced for both occlusion mapping and texture mapping by representing (1/w), (u/w) and (v/w) values in a block-fixed format.

Abstract: An MPEG decoding system in a host system, including software instructions for decoding a first portion of MPEG encoded data, including instructions for extracting macroblock data from said MPEG encoded data and for establishing a decoding order for said macroblock data. The system further includes hardware for extracting motion vector data and display data from said macroblocks. An entropy decoder for decoding encoded AC coefficients and DC coefficients in said display data is provided. An inverse quantization unit inversely quantizing said coefficients into a resulting array of decoded AC coefficients is also provided. An de-zig-zag unit scans said array of decoded AC coefficients and DC coefficients in a zig-zag pattern to provide a block of discrete cosine transformed coefficients. A inverse discrete cosine transform unit takes the inverse discrete cosine transform of the block of discrete cosine transformed coefficients to provide a first set of pel data.

Abstract: Copy-protected optical disk format, optical disk recording apparatus for creating disks having such formats and optical disk reading apparatus for reading disks having such formats and for determining whether the disks are authentic. In one aspect, an authentic optical disk has data bit indications along a spiral centerline of the disk, and these data bit indications define a radial wobble which has substantially greater energy at a predefined frequency f.sub.CPW (such as f.sub.CC /392) than at a frequency of f.sub.CC /196, where f.sub.CC is the spatial channel clock frequency. In another aspect, an authorized optical disk has data bit indications along a substantially spiral centerline of the disk, according to a channel clock whose frequency varies across the disk. The disk further has stored thereon an indication of the number of such channel clock cycles which occur along a predetermined test segment of the centerline, optionally together with a pointer to the test segment.

Abstract: A system and method for controlling a real-time rendering engine includes a control program for defining in regions of system memory a block header and a list of flow-control instructions.

Abstract: A process for decoding MPEG encoded image data stored in a system memory utilizing a configurable image decoding apparatus.

Abstract: A digital signal processing architecture is inherently cyclical in nature, by providing a timer which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input sample stream. Pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers. The processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO.