Abstract: A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.

Abstract: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: The present invention relates to a low pass filter incorporating coupled inductors to enhance stop band attenuation. In one embodiment, the coupled inductors are provided along with various capacitors to provide for superior performance within a smaller surface area of a semiconductor or ceramic integrated device. In a further specific embodiment, the capacitors are formed on an integrated device within an area on which entirely intertwined inductors are formed. In another embodiment, at least one further pair of coupled inductors is included to create additional frequency attenuation notches, as well as a wide stop-band.

Abstract: A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: The present invention describes ESD apparatus, methods of forming the same, and methods of providing ESD protection. In certain aspects, the invention achieves the desired turn-on voltage and maintains low leakage in the ESD apparatus, and the methods of providing ESD protection. In one aspect, a zener diode that has a positive trigger voltage is used to quickly turn-on a transistor. In another aspect, different zener diodes that have positive and negative trigger voltages, respectively, are used to quickly turn on a transistor. In still another aspect, a linearly graded P-region is used to implement the ESD device of the present invention.

Abstract: A manufacturing method of a semiconductor device with a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.

Abstract: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.

Abstract: A constant current output charge pump includes a switch module configured to compare a reference voltage with a load voltage and output a switch signal, a voltage margin control module configured to compare a first voltage and a second voltage with an output voltage and output a voltage margin control signal, a clock control module, a charge pump module, a current control module and a load module. The clock control module is configured to capture the switch signal and the voltage margin control signal and output a first clock signal and a second clock signal according to a system to the charge pump module for charging the input voltage.

Abstract: A method and apparatus wherein a material or object to be tested is placed on a base support. A stopper assembly having a stopper tip on one end in contact with the test material or object, and a washer on the opposite end attached to a rod. A projectile is propelled with a selected level of force along the rod and impacts the washer, which transmits the force of impact through the stopper tip to the test material or object. The level of propelling force, the mass of the projectile, the construction of the stopper assembly and the location of impact on the test material or object may be precisely adjusted to simulate real-life impacts.

Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Abstract: A constant current output charge pump includes a switch module configured to compare a reference voltage with a load voltage and output a switch signal, a voltage margin control module configured to compare a first voltage and a second voltage with an output voltage and output a voltage margin control signal, a clock control module, a charge pump module, a current control module and a load module. The clock control module is configured to capture the switch signal and the voltage margin control signal and output a first clock signal and a second clock signal according to a system to the charge pump module for charging the input voltage.

Abstract: The low-power power-on reset circuit includes a NOT gate device, a time delay device, a wave shaping device and a NOR gate device, with which the present invention can provide a low power power-on reset circuit that can be formed by a complementary metal oxide semiconductor (CMOS), such that a lower power consumption and a higher noise margin can both be provided.

Abstract: A method and apparatus wherein a material or object to be tested is placed on a base support. A stopper assembly having a stopper tip on one end in contact with the test material or object, and a washer on the opposite end attached to a rod. A projectile is propelled with a selected level of force along the rod and impacts the washer, which transmits the force of impact through the stopper tip to the test material or object. The level of propelling force, the mass of the projectile, the construction of the stopper assembly and the location of impact on the test material or object may be precisely adjusted to simulate real-life impacts.

Abstract: A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: A plurality of constant ON-time buck converters are coupled to a common load. The output of each buck converter is coupled to a common load via a series sense resistor. The regulated output voltage across the common load is compared to a reference voltage to generate a start signal. The start signal is alternately coupled to the controller on each buck converter. The ON-time of a master buck converter is terminated when a ramp signal generated from the regulator input voltage exceeds the reference voltage. All other slave converters have an ON-time pulse started by the start signal and stopped by comparing a sense voltage corresponding to their output current during their ON-time pulse to the peak current in the master converter during its ON-time. A counting circuit with an output corresponding to each of the plurality of buck converters is used to select which buck converter receives the start signal.

Abstract: A regulator circuit for use with integrated circuits protects downstream devices from the application of unregulated voltages during start-up or other initialization. The circuit includes an op amp which controls a regulator during steady state operation, and also includes a switching portion which responds to a reset signal and disconnects the op amp from the voltage regulator to prevent unregulated voltages from reaching the output node during start-up. During start-up, a current mirror is used to supply an initial voltage reference to the op amp, and upon establishment of steady state operation, the regulator turns off the current mirror and reconnects the op amp to the voltage regulator to allow the op amp and voltage regulator to control the output node.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as an inverter unit coupling the transmission line to stabilizing capacitors for stabilizing control node voltages.

Abstract: A method for endowing an integrated passive device array structure with a programmable value during manufacturing. The method includes forming a substantially conductive first layer and forming a plurality of passive device array elements of the integrated passive device array structure above the substantially conductive first layer. The method further includes forming an insulating layer above the plurality of passive device array elements. There is further included selectively forming vais the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.