Abstract: A constant current output charge pump includes a switch module configured to compare a reference voltage with a load voltage and output a switch signal, a voltage margin control module configured to compare a first voltage and a second voltage with an output voltage and output a voltage margin control signal, a clock control module, a charge pump module, a current control module and a load module. The clock control module is configured to capture the switch signal and the voltage margin control signal and output a first clock signal and a second clock signal according to a system to the charge pump module for charging the input voltage.

Abstract: The low-power power-on reset circuit includes a NOT gate device, a time delay device, a wave shaping device and a NOR gate device, with which the present invention can provide a low power power-on reset circuit that can be formed by a complementary metal oxide semiconductor (CMOS), such that a lower power consumption and a higher noise margin can both be provided.

Abstract: A method and apparatus wherein a material or object to be tested is placed on a base support. A stopper assembly having a stopper tip on one end in contact with the test material or object, and a washer on the opposite end attached to a rod. A projectile is propelled with a selected level of force along the rod and impacts the washer, which transmits the force of impact through the stopper tip to the test material or object. The level of propelling force, the mass of the projectile, the construction of the stopper assembly and the location of impact on the test material or object may be precisely adjusted to simulate real-life impacts.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: A method for fabricating a low dynamic resistance capacitor is an integrated circuit using conventional CMOS processing steps, where in one implementation the structure provides the additional feature of a Zener diode capable of offering ESD protection.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage as well as stabilizing capacitors for stabilizing control node voltages.

Abstract: An active termination circuit having a selective DC power consumption for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage. The circuit also has a variable current supply coupled to said first threshold reference transistor and said second threshold reference transistor arranged to reduce the DC power consumption of the active termination circuit as needed.

Abstract: An active termination circuit for clamping signals on a bus in an electronic device is described. The active termination circuit is configured to clamp the signals on the bus to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes bottom clamping transistors coupled to a first potential having bottom clamping transistor control nodes arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes top clamping transistors coupled to a second potential having top clamping transistor control nodes arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. In one embodiment, the active termination circuit includes a bottom clamping transistor coupled to a first potential having a bottom clamping transistor control node arranged for clamping the signal at about a first reference voltage. The active termination circuit also includes a top clamping transistor coupled to a second potential having a top clamping transistor control node arranged for clamping the signal at about a second reference voltage.

Abstract: An active termination circuit for protecting a node against an ESD voltage spike is described. The ESD protection circuit includes a bottom ESD protection transistor having a first node coupled to a first potential and a bottom ESD protection transistor intrinsic diode reverse biasedly coupling said node to a first reference voltage supply and a bottom threshold reference transistor coupled to the first reference voltage supply. The bottom threshold reference transistor provides a first bias voltage to the bottom ESD protection transistor gate that biases the bottom clamping transistor gate at about a first threshold voltage from the first reference voltage representing a threshold voltage of said bottom ESD protection transistor.

Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor.

Abstract: An active termination circuit for terminating a transmission line in bused or networked device, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: A voltage source switching circuit having switches capable of switching between different voltage sources with reduced voltage drop levels is disclosed. A selected one of the different voltage levels is output to a peripheral circuit or supplied to internal circuitry. In one embodiment, the switches are FET devices.

Abstract: The present invention relates, in one embodiment, to an integrated circuit including a first circuit structure, a first conductive bonding pad coupled to the first circuit structure, a second circuit structure, and a second conductive bonding pad coupled to the second circuit structure. The first conductive bonding pad is arranged to be separated from the second bonding pad by a gap having a gap dimension. The gap dimension is configured to be bridged by a wire bond, thereby permitting the wire bond to electrically couple the first conductive bonding pad with the second conductive bonding pad when the wire bond is coupled to the first bonding pad and the second bonding pad at the gap.

Abstract: An integrated electrical overload protection device and method of formation which functions as a thermal fuse. The device is integrated directly on the underlying structural or foundational material of an electrical circuit which experiences the electrical overstress. The device can be formed according to standard semiconductor process steps when formed on a semiconductor substrate. The device, or fuse, includes a first and second contact area separated by a gap area. A least a portion of the upper surfaces of the contact areas are covered with a wettable material such as gold. A solder bump, or bridge, is applied which spans the contact areas and provides an closed electrical connection. Upon application of an overload condition across the bridge material, a rise in temperature causes the solder material to melt. The solder flows onto the wettable areas and is drawn out of the gap area to thereby disrupt the electrical connection between the contact areas.

Abstract: A thin film protected capacitor structure having a thin film capacitor and a protection device is provided on an integrated circuit wafer. The wafer has a low resistivity substrate of a first type disposed under an epitaxial layer of a second type different from the first type. The structure includes a first heavily doped region, which is of the first type, in and through the epitaxial layer, and an oxide layer having a first oxide region disposed above the first heavily doped region. The first heavily doped region and the low resistivity substrate form the first plate of the thin film capacitor. There is also included a metal layer disposed above the first oxide region. A portion of this metal layer forms the second plate of the thin film capacitor. Between the second plate and the first plate, the aforementioned first oxide region represents the insulating dielectric. There is also included a second heavily doped region in the epitaxial layer.

Abstract: An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: An active termination circuit for terminating a transmission line in an electronic device. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor.

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention.

Abstract: A Quarter Size Small Outline Packages (QSOP) integrated resistor/capacitor network. The QSOP integrated resistor/capacitor network includes resistor/capacitor filters implemented in a QSOP package in integrated form. In one embodiment, the QSOP integrated resistor/capacitor network includes at least six ground pins for coupling capacitors of the resistor/capacitor filters with a common ground to maximize the attenuation of ultra-high frequency signals filtered through the resistor/capacitor filters.