Abstract: An active termination circuit for clamping a signal on a transmission line in an electronic device is described. The active termination circuit is configured to clamp the signal on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a bottom clamping transistor having a bottom clamping transistor first node coupled to a transmission line at a transmission line node, a bottom clamping transistor second node coupled to a first potential, and a bottom clamping transistor control node coupled to a first bias voltage supply. The circuit also includes a top clamping transistor having a top clamping transistor first node coupled to the transmission line at the transmission line node, a top clamping transistor second node coupled to a second potential, and a top clamping transistor control node coupled to a second bias voltage supply.

Abstract: A low drop-out regulator and methods for producing a low drop-out voltage are provided. A driver transistor adapted for connecting to an input supply voltage and producing an output voltage is provided. In addition, a mirroring transistor is coupled to the driver transistor and a voltage differential between the drain and the source of the driver transistor is mirrored in the mirroring transistor. The low drop-out regulator operates in both linear and saturation regions of the driver transistor. The driver transistor and the mirroring transistor are implemented in a CMOS process.

Abstract: An integrated passive device array structure with a value that is programmable during manufacturing. The device structure includes a substantially conductive first layer having a plurality of passive device array elements of the integrated passive device array structure disposed above the substantially conductive first layer. The device further includes an insulating layer formed above the plurality of passive device array elements. One or more vias are selectively formed in the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.

Abstract: Methods and apparatus for providing a rail-to-rail op amp are disclosed. The rail-to-rail op amp includes a P-channel input stage and an N-channel input stage. The P-channel input stage includes a set of P-channel MOS transistors and the N-channel input stage includes a set of N-channel MOS transistors. The set of N-channel MOS transistors and the set of P-channel MOS transistors are capable of connecting to an inverting input and a non-inverting input. The op amp further includes a mirroring circuit adapted for sensing current flowing through the P-channel input stage and mirroring a portion of the sensed current. A threshold voltage reduction circuit is adapted for reducing the threshold voltage of the P-channel input stage in proportion to the mirrored current.

Abstract: A method for endowing an integrated passive device array structure with a programmable value during manufacturing. The method includes forming a substantially conductive first layer and forming a plurality of passive device array elements of the integrated passive device array structure above the substantially conductive first layer. The method further includes forming an insulating layer above the plurality of passive device array elements. There is further included selectively forming vais the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.

Abstract: A semiconductor device which has a resistor, a capacitor, a Schottky diode, and an ESD protection device all formed on a single semiconductor substrate. The resistor and the capacitor are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor and capacitor.

Abstract: A semiconductor device which has a resistor, a capacitor, a Schottky diode, and an ESD protection device all formed on a single semiconductor substrate. The resistor and the capacitor are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor and capacitor.

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention.

Abstract: A method for endowing an integrated passive device array structure with a programmable value during manufacturing. The method includes forming a substantially conductive first layer and forming a plurality of passive device array elements of the integrated passive device array structure above the substantially conductive first layer. The method further includes forming an insulating layer above the plurality of passive device array elements. There is further included selectively forming vais the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.