Patents Assigned to Calogic Corporation
  • Patent number: 5798549
    Abstract: In a gated semiconductor device, a doped polysilicon layer overlies an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to contact the underlying substrate. The dopants implanted in the polysilicon layer are diffused into the underlying substrate to form the source region in a self-aligned process which requires no extra masking step. The doped polysilicon layer, by contacting the source region and also overlying the gate, allows external electrical contact to be made directly to the doped polycrystalline silicon layer and to the surface of the substrate, eliminating the need for a special source contact adjacent to the gate. This conserves surface area of the device, allowing fabrication of a smaller and hence more economical device.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: August 25, 1998
    Assignee: Calogic Corporation
    Inventor: Richard A. Blanchard
  • Patent number: 5663079
    Abstract: In a method of fabricating semiconductor devices such as transistors and in the devices formed thereby, a doped polysilicon layer is formed overlying an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to contact the underlying substrate. The dopants implanted in the polysilicon layer are diffused into the underlying substrate to form the source region in a self-aligned process which requires no extra masking step. The doped polysilicon layer, by contacting the source region and also overlying the gate, allows external electrical contact to be made on the top of the gate to the source regions, eliminating the need for a special source contact adjacent to the gate. This conserves surface area of the device, allowing fabrication of a smaller and hence more economical device.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 2, 1997
    Assignee: Calogic Corporation
    Inventor: Richard A. Blanchard
  • Patent number: 5528063
    Abstract: In a gated semiconductor device, a doped polysilicon layer overlies an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to contact the underlying substrate. The dopants implanted in the polysilicon layer are diffused into the underlying substrate to form the source region in a self-aligned process which requires no extra masking step. The doped polysilicon layer, by contacting the source region and also overlying the gate, allows external electrical contact to be made directly to the doped polycrystalline silicon layer and to the surface of the substrate, eliminating the need for a special source contact adjacent to the gate. This conserves surface area of the device, allowing fabrication of a smaller and hence more economical device.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: June 18, 1996
    Assignee: Calogic Corporation
    Inventor: Richard A. Blanchard
  • Patent number: 4734609
    Abstract: An improved gas density transducer which compares the resonant frequency of an enclosed, reference tuning fork crystal oscillator with the resonant frequency of a detector tuning fork crystal oscillator exposed to the surrounding gas. The frequency of oscillation of the detector crystal oscillator exposed will vary in accordance with the gas density because of the motional resistance of the gas to vibrations of the tuning fork oscillator. The frequency of the detector oscillator can be compared to the frequency of the reference oscillator to determine the gas density.
    Type: Grant
    Filed: July 25, 1986
    Date of Patent: March 29, 1988
    Assignee: Calogic Corporation
    Inventor: Richard Jasmine