Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing formal verification of circuit descriptions. In certain example embodiments, the disclosed technology involves the formal verification of a register-transfer-level (“RTL”) circuit description produced from a high level synthesis tool (e.g., a C++ or SystemC synthesis tool) relative to the original high level code from which the RTL description was synthesized (e.g., the original C++ or SystemC description) using sub-functional-call-level transactions.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output.

Abstract: A system, method and computer program product are provided for altering a hardware description based on an instruction file. In use, a hardware description is identified. Additionally, the hardware description is analyzed. Further, an instruction file is created based on the analysis. Moreover, the hardware is altered based on the instruction file.

Abstract: A system, method and computer program product are provided for reducing a deactivation function utilizing an optimal reduction. In use, a deactivation function is identified. Additionally, reductions for the deactivation function are calculated. Further, an optimal reduction of the calculated reductions is determined. Moreover, the deactivation function is reduced, utilizing the optimal reduction.

Abstract: Methods and apparatuses for verifying a concurrent logical design and a corresponding non-sequential algorithmic description are provided. In some implementations, verification of a non-sequential algorithmic description for a device design is facilitated by monitoring a simulation of the non-sequential algorithmic description and synchronizing the timing of selected events with timing from an already completed simulation of a corresponding logical design. With various implementations, the hierarchical blocks in the logical design are monitored during the prior simulation to record selected event information. Subsequently, the recorded event information may be used to synchronize the simulation of the non-sequential algorithmic description.

Abstract: An algorithmic programming language approach to system design enables design, synthesis, and validation of structured, system-level specifications, and integrates system-level design into the rest of the design process. The algorithmic programming language design approach includes various techniques and tools, which can be used in combination or independently. For example, the design approach includes techniques and tools for simplifying specification of a design unit interface in a programming language specification and/or simplifying specification of synchronization and sub-design unit concurrency for a design unit. According to a first aspect of the design approach, design occurs at the algorithmic level of abstraction. According to a second aspect, the design approach leverages existing simulation technology for validation at various stages of the design flow.

Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, the transformation identifies a word-level functionality of the at least some of the finite portions by converting bit-level functionality into word-level functionality.

Abstract: A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at least some of the finite portions are transformed, utilizing at least one predetermined transformation. Further, an equivalence of the netlist and another netlist is determined, utilizing at least a subset of the finite portions and the infinite portions. Moreover, an abstraction is performed on the netlist.

Abstract: A system, method and computer program product are provided for optimizing an altered hardware design utilizing power reports. In use, a first hardware design is synthesized. Additionally, a first power report is generated for the synthesized first hardware design. Further, the first hardware design is altered. Further still, the altered hardware design is synthesized. Also, a second power report is generated for the synthesized altered hardware design. Furthermore, the altered hardware design is optimized utilizing the first power report and the second power report.

Abstract: An integrated circuit design system, method, and computer program product are provided that takes into account signal stability. In use, at least one condition is identified where an output of a logic element before receipt of a clock signal is the same as the output of the logic element after receipt of the clock signal. To this end, such logic element may be disabled based on the identified condition for power savings or other purposes.

Abstract: An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.

Abstract: A mapping system, method and computer program product are provided. In use, at least one arithmetic operator is received. Further, the at least one arithmetic operator is mapped to at least one cell, at a word-level.

Abstract: A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to generate output. To this end, sequential equivalence of the first system and the second system may be verified, based on the output.

Abstract: A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells are identified for each data operator, simultaneously with technology mapping. By this design, at least one of the cells may thus be selected for design optimization purposes.

Abstract: A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking, sequential differences between a first design and a second design are identified. It is then determined whether the first design and the second design are equivalent, utilizing the identified sequential differences.

Abstract: A system, method and computer program product are provided for generating and manipulating a compressed data structure. Initially, a plurality of values associated with an ordered collection of bits is received. It is then determined which of the values are the same. To this end, a compressed data structure including the values is generated, based on the determination.

Abstract: A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.

Abstract: A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.