Abstract: A multilayer ceramic, multi-chip, dual in-line packaging assembly comprises a ceramic substrate with a pair of semiconductor chip receiving cavities therein. A metalization pattern partially embedded within the substrate provides electrical paths for semiconductor chip devices joined thereto to external circuitry. Semiconductor chips are joined to exposed pads within the chip receiving cavities. Metalization spaced from and positioned beneath the semiconductor chip devices completes interconnections between semiconductor chip devices. Exposed finger areas are spaced from one another and about the semiconductor chip receiving cavities. Embedded lines extend from the finger areas to external circuitry and interconnection means extend between finger areas.