Abstract: A data processing arrangement including a microprocessor and a plurality of input/output devices arranged in groups in accordance with a predetermined priority scheme. Each input/output device is capable of initiating a service request via an interrupt line to the microprocessor as a result of which a machine cycle is initiated by the microprocessor in which control signals are produced by the microprocessor and applied to logic circuitry coupled to the groups of input/output devices. The logic circuitry operates to propagate a low voltage level at the output of the input/output device initiating the service request down through the lower priority groups and to change inputs of the lower priority input/output devices from normal high voltage levels to low voltage levels. Data is then applied by the input/output device initiating the service request to the microprocessor, following which a microprocessor reset instruction resets the device.