Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e., the higher the heat dissipation efficiency of the region where the adjacent heating components are located is, the smaller the space between the adjacent heating components in the region will be, the heat dissipation efficiencies corresponding to the heating components are balanced, and load of a fan is reduced.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e., the higher the heat dissipation efficiency of the region where the adjacent heating components are located is, the smaller the space between the adjacent heating components in the region will be, the heat dissipation efficiencies corresponding to the heating components are balanced, and load of a fan is reduced.

Abstract: Disclosed is a frame, comprising a frame body and a control module. The frame body comprises a bottom plate, a top plate and a side plate, wherein the side plate is supported between the bottom plate and the top plate; a power source module accommodation area and a computing module accommodation area are defined between the bottom plate and the top plate; the bottom plate is provided with a frame slideway; and a power source module and a computing module respectively enter and exit by means of the frame slideway, and are fixed in the power source module accommodation area and the computing module accommodation area. The control module is connected to the top plate. The aim of the present invention is to provide a frame, which is used for an integrated computing unit, and which has a small and lightweight structure, a rational layout and is low cost.

Abstract: Disclosed is an immersed liquid cooling heat dissipation system, which comprises a liquid cooling module, an oil path circulation device, and a plurality of computing devices to undergo heat dissipation. Each computing device comprises a frame, a control module, a power module, and computing modules. The liquid cooling module comprise a first device slot tank, a second device slot tank, a return flow slot tank, and a flow-equalizing plate. The return flow slot tank is located between the first device slot tank and the second device slot tank, wherein the flow-equalizing plate is disposed in the first device slot tank and the second device slot tank, and the computing devices are disposed on the flow-equalizing plate. The frame is internally provided with a power module accommodating region used for accommodating the power module and a computing module accommodating region used for accommodating the computing module.

Abstract: A waste heat utilization system of an immersed liquid cooling heat dissipation device. The immersed liquid cooling heat dissipation device (100) comprises a liquid cooling tank (110). The liquid cooling tank (110) comprises an oil tank inlet (111) and an oil tank outlet (112). The system further comprises a waste heat utilization device (200). The waste heat utilization device (200) comprises a waste heat utilization body (210), a cold oil outlet (220) and a hot oil inlet (230), the cold oil outlet (220) and the hot oil inlet (230) being connected to the waste heat utilization body (210); the cold oil outlet (220) is connected with the oil tank inlet (111); the hot oil inlet (230) is connected to the oil tank outlet (112); the waste heat utilization body (210) is connected to a heat utilization end (300).

Abstract: The invention provides a chip frequency modulation method and apparatus of a computing device, a hash board, a computing device and a storage medium. The chip frequency modulation method comprises: setting a plurality of working frequencies for the operational chip and causing the plurality of cores work at the respective working frequencies; analyzing a computing performance indicator of each core at its current working frequency; and modulating the current working frequency of the core up or down according to the computing performance indicator of the core modulating the frequency of a core with high computing performance up and modulating the frequency of a core with low computing performance down. Therefore, the invention can automatically modulate a frequency corresponding to each core according to the actual computing performance of each core in the operational chip of the computing device, thereby maximizing the computing performance of the cores.

Abstract: The invention provides a voltage-following series power supply circuit, comprising a power supply end and a ground end; a power supply module comprising an input end connected to the power supply end, and an output end for providing a power supply to two or more to-be-powered chips, the power supply module and the to-be-powered chips connected in series between the power supply end and the ground end; and at least one auxiliary power supply module for supplying an auxiliary power supply to the to-be-powered chips, wherein a voltage following module is further connected between the power supply end and the auxiliary power supply module for adjusting a voltage of the auxiliary power supply.

Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. The computing device of the disclosure includes a device housing enclosing an enclosed heat-dissipation air duct, and the computational heat dissipation structure; the computational heat dissipation structure is located in the enclosed heat-dissipation air duct. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e.

Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A printed circuit board structure and a wiring method therefor are disclosed. The printed circuit board structure comprises a first wiring channel formed inside the printed circuit board for transmitting a circuit signal; a pin, connected to the first wiring channel for connecting a chip to the printed circuit board; the pin comprising an unused pin and a used pin, the used pin comprising a peripheral pin and an internal pin; wherein the printed circuit board further comprises a second wiring channel, the second wiring channel leads out the internal pin by means of covering at least a portion of the unused pin. By means of using a printed circuit board structure and a wiring method to configure pins of the printed circuit board, the number of printed circuit board layers is reduced, and the current carrying capacity is enhanced.